M41ST95WMH6TR STMICROELECTRONICS [STMicroelectronics], M41ST95WMH6TR Datasheet - Page 10

• Manufacturer Part Number: M41ST95WMH6TR
• Description: 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M41ST95Y*, M41ST95W
Signal Description
Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI). The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each re-
ceived this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL). The serial clock provides the
timing for the serial interface (as shown in
9., page 11
Bit, addresses, or data are latched, from the input
pin, on the rising edge of the clock input. The out-
put data on the SDO pin changes state after the
falling edge of the clock input.
Table 2. Function Table
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 8. Data and Clock Timing
10/35
Disable Reset
CPOL
WRITE
READ
Mode
0
1
and
CPHA
0
1
Figure 10., page
SDO
SCL
SCL
SDI
H
E
L
L
11). The W/R
MSB
MSB
Figure
Input Disabled
AI04630
AI04631
SCL
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table
Chip Enable (E). When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is re-
quired prior to the start of any operation.
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
Input Disabled
Data Bit latch
SDI
X
2
and Figure 8).
Next data bit shift
LSB
LSB
High Z
High Z
SDO
AI06368
(1)