M41ST95WMH6TR STMICROELECTRONICS [STMicroelectronics], M41ST95WMH6TR Datasheet - Page 9

• Manufacturer Part Number: M41ST95WMH6TR
• Description: 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

OPERATION
The M41ST95Y/W clock operates as a slave de-
vice on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI
bus compatible. The bus signals are SCL, SDI and
SDO (see
The device is selected when the Chip Enable input
(E) is held low. All instructions, addresses and
data are shifted serially in and out of the chip. The
most significant bit is presented first, with the data
input (SDI) sampled on the first rising edge of the
clock (SCL) after the Chip Enable (E) goes low.
The 64 bytes contained in the device can then be
accessed sequentially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20.
21 - 64.User RAM
The M41ST95Y/W clock continually monitors V
for an out-of tolerance condition. Should V
below V
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
V
CC
rises above V
Square Wave Register
CC
PFD
Table 1., page 5
falls below V
, the device terminates an access in
SO
, the battery is disconnected,
SO
and
, the device automati-
Figure 7., page
CC
fall
8).
CC
and the power supply is switched to external V
Write protection continues until V
V
on Battery Storage Life refer to Application Note
AN1012.
SPI Bus Characteristics
The Serial Peripheral interface (SPI) bus is intend-
ed for synchronous communication between dif-
ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41ST95Y/W) devices.
The SCL input, which is generated by the micro-
controller, is active only during address and data
transfer to any device on the SPI bus (see
7., page
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see
ure 8., page
There is one clock for each bit transferred. Ad-
dress and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
PFD
(min) plus t
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
8).
10).
REC
M41ST95Y*, M41ST95W
(min). For more information
Table 2., page 10
CC
and
reaches
Figure
Fig-
9/35
CC
.