M41ST95WMH6TR STMICROELECTRONICS [STMicroelectronics], M41ST95WMH6TR Datasheet - Page 23

• Manufacturer Part Number: M41ST95WMH6TR
• Description: 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to tog-
gle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit and Watchdog Register
are not set, the IRQ/FT/OUT pin becomes an out-
put driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ/FT/OUT pin will be driven low.
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Battery Low Warning
The M41ST95Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
Table 8. t
Note: 1. Default Setting; after oscillator has started
Table 9. Default Values
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
Initial Power-up (Battery Attach
for SNAPHAT)
Subsequent power-up (with
battery back-up)
t
2. State of other control bits undefined.
3. UC = Unchanged.
REC
Bit (TR)
REC
0
0
1
Condition
(2)
Definitions
(3)
STOP Bit (ST)
X
0
1
UC
TR
0
UC
ST
0
HT
1
1
Min
96
40
50
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT
may be replaced while V
The M41ST95Y/W only monitors the battery when
a nominal V
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
t
Bit D7 of Clock Register 04h contains the t
(TR). t
the deselect time after V
lows for a voltage setting time before WRITEs may
again be performed to the device after a power-
down condition. The t
set the length of this deselect time as defined by
Table 8.
Preferred Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watch-
dog Register, TR, FT, AFE, ABE, and SQWE. The
following bits are set to a '1' state: OUT and HT
(see Table 9).
Out
REC
UC
1
t
REC
Bit
REC
Time
FT
0
0
refers to the automatic continuation of
CC
is applied to the device. Thus appli-
AFE
2000
0
0
98
Max
200
(1)
M41ST95Y*, M41ST95W
REC
ABE
0
0
CC
CC
Bit will allow the user to
reaches V
applied to the device.
SQWE
0
0
Units
WATCHDOG
PFD
Register
ms
ms
µs
. This al-
0
0
REC
CC
®
23/35
(1)
top
Bit
is