AD9865CHIPS AD [Analog Devices], AD9865CHIPS Datasheet - Page 10

• Manufacturer Part Number: AD9865CHIPS
• Description: Broadband Modem Mixed-Signal Front End
• Manufacturer: AD [Analog Devices]

AD9865
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.
1
2 to 5
6
7
8, 9
10
11
12
13
14
TXCLK/TXQUIET
RXEN/RXSYNC
TXEN/TXSYNC
Mnemonic
ADIO9
Tx[5]
ADIO8 to 5
Tx[4 to 1]
ADIO4
Tx[0]
ADIO3
Rx[5]
ADIO2, 1
Rx[4, 3]
ADIO0
Rx[2]
NC
Rx[1]
NC
Rx[0]
RXEN
RXSYNC
TXEN
TXSYNC
ADIO3/Rx[5]
ADIO2/Rx[4]
ADIO1/Rx[3]
ADIO0/Rx[2]
ADIO9/Tx[5]
ADIO8/Tx[4]
ADIO7/Tx[3]
ADIO6/Tx[2]
ADIO5/Tx[1]
ADIO4/Tx[0]
NC/Rx[1]
NC/Rx[0]
RXCLK
13
10
11
12
14
15
16
2
3
4
5
6
8
9
1
7
17
64
PIN 1
IDENTIFIER
18
63
19
62
Mode
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
20
61
Figure 2. Pin Configuration
21
60
Rev. A | Page 10 of 48
1
22
59
(Not to Scale)
AD9865
TOP VIEW
23
58
Description
MSB of ADIO Buffer
MSB of Tx Nibble Input
Bits 8 to 5 of ADIO Buffer
Bits 4 to 1 of Tx Nibble Input
Bit 4 of ADIO Buffer
LSB of Tx Nibble Input
Bit 3 of ADIO Buffer
MSB of Rx Nibble Output
Bits 2 to 1 of ADIO Buffer
Bits 4 to 3 of Rx Nibble Output
LSB of ADIO Buffer
Bit 2 of Rx Nibble Output
No Connect
Bit 1 of Rx Nibble Output
No Connect
LSB of Rx Nibble Output
ADIO Buffer Control Input
Rx Data Synchronization Output
Tx Path Enable Input
Tx Data Synchronization Input
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
36
47
46
45
44
43
41
40
39
38
37
35
34
33
48
42
AVSS
AVSS
IOUT_N–
IOUT_G–
AVSS
AVDD
REFIO
REFADJ
AVDD
AVSS
RX+
RX–
AVSS
AVDD
AVSS
REFT