AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 23

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
DAC CONTROL REGISTER
The DAC Control Register is used to configure each DAC Channel. The DAC Control Register is selected by setting bits CREG2, CREG1,
CREG0 to 0,1,0.
Table 21. Programming DAC Control Register
D15
0
Table 22. DAC Control Register Functions
Option
RSET
R2,R1,R0
OVRNG
INT_ENABLE
CLR_EN
OUTEN
DC_DC
SOFTWARE REGISTER
The Software Register has three functions. It allows the user to perform a software reset to the part. It can be used to set bit D11 in the
Status Register. Lastly it is also used as part of the watchdog feature to ensure that the SPI interface connections are working properly. To
ensure all the datapath lines are working properly (i.e. SDI/SCLK/SYNC), the user must write 0x195 to the Software Register within the
timeout period. If this command is not received within the timeout period, the ALERT pin will signal a fault condition. Note. This is only
required when the Watchdog Timer function is enabled.
Table 23. Programming the Software Register
To program a software reset you need to write 1,0,0 to CREG2, CREG1, CREG0.
MSB
D15
1
D14
1
D14
0
D13
0
D13
D12
X
0
D11
X
User Program Bit
Can only be done on a per channel basis.
Enables/Disables the selected output channel
OUTEN=1, Enables channel
OUTEN=0, Disable channel
Description
Selects internal or external current sense resistor for selected DAC channel
RSET = 0 Selects external Resistor
RSET = 1 Selects Internal Resistor
Selects output range enabled.
Enables 20% overrange on Vout Channel only. No current overrange available.
OVRNG=1, Enabled
OVRNG=0, Disabled
Powers up the DC-DC, DAC and internal amplifiers for the selected channel. Does not enable the output.
Per channel Clear Enable bit. Selects if this channel will clear when the CLEAR pin is activated.
CLR_EN=1, channel will clear when part is cleared.
CLR_EN=0, channel will not clear when part is cleared.
Powers the DC-DC on selected channel.
DC_DC = 1, Power up DC_DC
DC_DC = 0, Power down DC_DC
This allows per channel DC_DC power up/down. To power down the DCDC, OUTEN and INT_ENABLE
bits must also be set to 0.
All DC-DCs can also be powered up simultaneously using DCDC_All bit in the Main Control Register.
D10
X
R2
0
0
0
0
1
1
1
D12
R1
0
0
1
1
0
0
1
D9
X
R0
0
1
0
1
0
1
0
D8
INT_ENABLE
Output Range Selected
0 to 5V Voltage Range
0 to 10V Voltage Range
±5V Voltage Range
±10V Voltage Range
4 to 20 mA Current Range
0 to 20 mA Current Range
0 to 24 mA Current Range
RESET CODE/SPI CODE
Rev. PrD | Page 23 of 34
D11 to D0
D7
CLR_EN
LSB
D6
OUTEN
D5
RSET
D4
DC-DC
D3
OVRNG
D2
R2
D1
R1
AD5755-1
D0
R0