AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 27

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
FEATURES
OUTPUT FAULT
The AD5755-1 is equipped with a FAULT pin, this is an active
low open-drain output allowing several AD5755-1 devices to be
connected together to one pull-up resistor for global fault
detection. The FAULT pin is forced active by any one of the
following fault scenarios;
The OPEN CCT and OVER TEMP bits of the Status Register
are used in conjunction with the FAULT output to inform the
user which one of the fault conditions caused the FAULT output
to be activated.
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation the voltage output will sink/source up
to 10mA and maintain specified operation. The maximum
current that the voltage output will deliver is 15mA, this is the
short circuit current. This short circuit current is programmable
by the user and can be set to 15mA or 8mA. If a short circuit is
detected the FAULT will go low and the relevant SHORT CCT
bit in the Status register will be set.
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) and offset (C) register, which
allow trimming out of the gain and offset errors of the entire
signal chain. Data from the DAC Data Register is operated on
by a digital multiplier and adder controlled by the contents of
1)
2)
3)
4)
The Voltage at I
compliance range, due to an open-loop circuit or
insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with “window limits” since this would
require an actual output error before the FAULT
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approximately one volt of remaining drive
capability. Thus the FAULT output activates slightly
before the compliance limit is reached. Since the
comparison is made within the feedback loop of the
output amplifier, the output accuracy is maintained by
its open-loop gain and an output error does not occur
before the FAULT output becomes active.
A short is detected on the voltage output pin. Short
circuit current limited to 15ma or 8ma, this is
programmable by the user.
An interface error is detected due to a PEC failure. See
Packet Error Checking section.
If the core temperature of the AD5755-1 exceeds
approx. 150°C.
OUT
attempts to rise above the
Rev. PrD | Page 27 of 34
the M and C registers. The calibrated DAC data is then stored
in the DAC2 register.
Although this diagram indicates a multiplier and adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all 4 channels. This has implications
for the update speed when several channels are updated at once.
Each time data is written to the M or C register the output is not
automatically updated. Rather, the next write to the DAC
channel will use these M&C values to perform a new calibration
and automatically update the channel.
Data output from the DAC2 register is routed to the final DAC
register by a multiplexer. Both the Gain Register and the Offset
Register have 16 bits of resolution. The correct method to
calibrate the gain/offset is firstly to calibrate out the gain and
then calibrate the offset.
The value (in decimal) that is written to the DAC register can
be calculated by:
where:
D is the code loaded to the DAC channels input register.
M is the code in Gain Register − default code = 2
C is the code in Offset Register − default code = 2
STATUS READBACK DURING WRITE
The AD5755-1 has the ability to read back the Status Register
contents during every write sequence. This feature is enabled
via the STATREAD bit in the Main Control Register. This
allows the user to continuously monitor the Status Register and
act quickly in the case of a fault.
When Status Readback During Write is enabled the contents of
the 16bit Status register (See Table 31) is outputted on the SDO
pin as indicated in Figure 4.
The AD5755-1 will power up with this feature disabled. When
this is enabled the normal readback feature is not available,
except of the status register. To readback any other register set
STATREAD low first before following the readback sequence.
STATREAD may be set high again after the register read.
Code
REGISTER
REGISTER
REGISTER
INPUT
DAC
M
C
Figure 19. Digital Offset and Gain control
Re
gister
=
D
×
(
M
2
16
+
) 1
REGISTER
+
DAC
C
−
AD5755-1
16
15
2
– 1
15
DAC