AD5755-1x AD [Analog Devices], AD5755-1x Datasheet - Page 24

• Manufacturer Part Number: AD5755-1x
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: AD [Analog Devices]

AD5755-1
Table 24. Software Register Functions
User Program Bit
RESET CODE/SPI CODE
DC-DC CONTROL REGISTER
The DC-DC Control Register allows the user control over the DC-DC Switching Frequency, and of the phase of when the per channel
switching starts. The maximum allowable DC-DC output frequency is also programmable.
Table 25. Programming the DC-DC Control Register
Table 26. DC-DC Control Register Options
Option
DC-DCMaxV
DC-DC Freq
DC-DC Phase
SLEW RATE CONTROL REGISTER
This register is used to program the slew rate control for the selected DAC Channel. The CREG bits are set to ‘0,0,0’ to select the Slew
Rate Control Register. SR_CLOCK and SR_STEP allow the user to control the rate of the output SLEW. This feature is available on both
the current and voltage outputs. With the slew rate control feature disabled the output value will change at a rate limited by the output
drive circuitry and the attached load. SE enables output slew rate control. It can be both programmed and enabled/disabled on a per
channel basis. For more information see the features section.
Table 27. Programming the Slew Rate Control Register
D15
0
MSB
D15
0
D14
0
D14
1
D13
0
D12
SE
D13
1
This bit is mapped to bit D11 of the Status Register. When this bit is set to 1 bit D11 of the Status Register is set to
1. Likewise when D12 is set to 0 bit D11 of the Status Register is also set to zero. This feature can be used to
ensure the SPI pins are working correctly by writing known bit to this register and reading back corresponding
bit from the Status Register.
Option
RESET CODE
SPI CODE
Description
Maximum allowed output Voltage of the DC-DC
00 = 25V ±1V
01 = 27.3 ±1V
10 = 28.6 ±1V
11 = 30 ±1V
User Programmable DC-DC Switching Frequency:
00 = 250 Khz
01 = 406 Khz
10 = 649 Khz
11 = 812 Khz
User Programmable DC-DC Phase (Between Channels)
00 = All DC-DCs clock on same edge
01 = ChanA, ChanB clock on same edge, ChanC & ChanD clock on opposite edge
10 = ChanA, ChanC clock on same edge, ChanB & ChanD on opposite edge
11 = ChanA,ChanB,ChanC, ChanD clock 90' out of phase from each other
D11-D7
X
D12 to D7
X
D6 to D3
SR_CLOCK
DC-DC Phase
D5 to D4
Description
Writing 0x555 to D11-D0 performs a reset.
If Watchdog Timer feature enabled, 0x195 must be written to the Software Register
(D11-D0) within every timeout period to ensure valid data communication path.
D2 to D0
SR_STEP
Rev. PrD| Page 24 of 34
DC-DC Freq
D3 to D2
LSB
DC-DC MaxV
D1 to D0
Preliminary Technical Data