AD5755-1_11 AD [Analog Devices], AD5755-1_11 Datasheet
AD5755-1_11
Related parts for AD5755-1_11
AD5755-1_11 Summary of contents
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... APPLICATIONS Process control Actuator control PLCs HART network connectivity GENERAL DESCRIPTION The AD5755 quad, voltage and current output DAC that operates with a power supply range from −26 +33 V. On-chip dynamic power control minimizes package power AV SS –15V/0V AGND DV ...
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... Typical Performance Characteristics ........................................... 15 Voltage Outputs .......................................................................... 15 Current Outputs ......................................................................... 19 DC-to-DC Block......................................................................... 23 Reference ..................................................................................... 24 General......................................................................................... 25 Terminology .................................................................................... 26 Theory of Operation ...................................................................... 28 DAC Architecture....................................................................... 28 Power-On State of the AD5755-1............................................. 28 Serial Interface ............................................................................ 29 Transfer Function ....................................................................... 29 Registers ........................................................................................... 30 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 31 Changing and Reprogramming the Range ............................. 31 Data Registers ............................................................................. 32 REVISION HISTORY 5/11—Rev Rev. A Removed Endnote 6 (Table 1) ...
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... DAC CHANNEL B AD1 DAC CHANNEL C AD5755-1 DAC CHANNEL D AD0 SW POWER 7.4V TO 29.5V CONTROL 16 DAC + DAC A REG A VOUT RANGE SCALING Figure 2. Rev Page AD5755 BOOST_A DC-TO-DC CONVERTER V V SEN1 SEN2 REG OUT_A R R1 SET_A CHARTA +V SENSE_A V OUT_A OUT_B ...
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... AD5755-1 SPECIFICATIONS −15 V BOOST_x SS GNDSW = 0 V; REFIN = 5 V; voltage outputs otherwise noted. Table 1. Parameter 1 Min VOLTAGE OUTPUT Output Voltage Ranges 0 0 −5 − −6 −12 ACCURACY BIPOLAR SUPPLY Resolution 16 Total Unadjusted Error (TUE) −0.04 −0.03 TUE Long-Term Stability Relative Accuracy (INL) − ...
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... The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compli- ance is not exceeded; see MaxV bits in 100 MΩ 0.02 1 μA/V Rev Page AD5755-1 = 150°C J SET = 25° 150° 25° 25° 25° 25° ...
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... AD5755-1 1 Parameter Min REFERENCE INPUT/OUTPUT 2 Reference Input Reference Input Voltage 4.95 DC Input Impedance 45 Reference Output Output Voltage 4.995 2 Reference TC −10 Output Noise (0 Hz Noise Spectral Density 2 Output Voltage Drift vs. Time 2 Capacitive Load Load Current Short-Circuit Current 2 Line Regulation Load Regulation ...
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... See test conditions/ ms comments 0.15 LSB p-p 0.5 nA/√Hz Rev Page AD5755-1 Test Conditions/Comments Voltage output mode on all channels, output unloaded, over supplies Current output mode on all channels Voltage output mode on all channels, output unloaded, over supplies Current output mode on all channels V ...
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... AD5755-1 TIMING CHARACTERISTICS − BOOST_x SS GNDSW = 0 V; REFIN = 5 V; voltage outputs otherwise noted. Table Parameter Limit MIN MAX 198 ...
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... Figure 3. Serial Interface Timing Diagram LSB MSB LSB MSB Figure 4. Readback Timing Diagram Rev Page LSB NOP CONDITION LSB SELECTED REGISTER DATA CLOCKED OUT AD5755-1 ...
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... AD5755 SCLK SYNC DUT_ DUT_ R/W X SDIN AD1 AD0 SDO SDO DISABLED X X DB15 DB14 SDO_ STATUS STATUS ENAB Figure 5. Status Readback During Write 200µ OUTPUT PIN 50pF 200µ Figure 6. Load Circuit for SDO Timing Diagram Rev ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION + using BOOST_x using BOOST_x using BOOST_x )/θ Rev Page AD5755-1 ...
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... Only channels enabled to be cleared are cleared. See the Device Features section for more information. When CLEAR is active, the DAC output register cannot be written to. PIN 1 1 SET_B 2 SET_A 3 4 AD0 5 AD1 6 SYNC 7 AD5755-1 SCLK 8 TOP VIEW SDIN 9 (Not to Scale) SDO LDAC 13 ...
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... Output Buffer. Connecting a 220 pF capacitor between OUT_B pin allows the voltage output to drive μF. Note that the addition of this capacitor OUT_B Supply Requirements—Slewing sections in the Device Features section for more CC Rev Page AD5755-1 . OUT_A stage, which is OUT_x . OUT_B ...
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... AD5755-1 Pin No. Mnemonic Description 46 V Supply for Channel C Current Output Stage (see Figure 73). This is also the supply for the V BOOST_C regulated the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80 Current Output Pin for DAC Channel C. OUT_C ...
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... Figure 12. Differential Nonlinearity Error vs. Temperature 0.012 +5V RANGE +10V RANGE 0.010 ±5V RANGE ±10V RANGE 0.008 AV = +15V DD 0.006 AV = –15V SS OUTPUT UNLOADED 0.004 0.002 0 –0.002 –0.004 –0.006 –40 – TEMPERATURE (°C) Figure 13. Total Unadjusted Error vs. Temperature AD5755 100 80 100 80 100 ...
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... AD5755-1 0 –0.005 –0.010 +5V RANGE –0.015 +12V RANGE AV = +15V DD –0.020 OUTPUT UNLOADED –0.025 –0.030 –0.035 –40 – TEMPERATURE (°C) Figure 14. Total Unadjusted Error vs. Temperature, Single Supply 0.012 +5V RANGE +10V RANGE 0.010 ±5V RANGE ± ...
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... –4 –8 –12 – Rev Page AD5755-1 8mA LIMIT, CODE = 0xFFFF 16mA LIMIT, CODE = 0xFFFF ±10V RANGE T = 25°C A –16 –12 –8 – OUTPUT CURRENT (mA +15V – ...
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... AD5755 –5 –10 –15 – TIME (µs) Figure 26. Digital-to-Analog Glitch +15V –15V SS ±10V RANGE 25°C A OUTPUT UNLOADED 5 0 –5 –10 – TIME (s) Figure 27. Peak-to-Peak Noise (0 Bandwidth) 300 ...
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... Rev Page AD5755-1 4mA TO 20mA RANGE MAX INL AV = +15V DD 0mA TO 24mA RANGE MAX INL AV = –15V/0V SS 0mA TO 20mA RANGE MIN INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MIN INL – ...
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... AD5755-1 0.03 0.02 0.01 0 –0. +15V DD –0. –15V/0V SS –0.03 4mA TO 20mA INTERNAL R –0.04 0mA TO 20mA INTERNAL R –0.05 0mA TO 24mA INTERNAL R 4mA TO 20mA EXTERNAL R –0.06 0mA TO 20mA EXTERNAL R 0mA TO 24mA EXTERNAL R –0.07 –0.08 –40 – TEMPERATURE (°C) Figure 38. Total Unadjusted Error vs. Temperature 0.03 0.02 0.01 0 –0.01 –0.02 ...
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... Figure 48. Output Current vs. Time on Output Enable SET –0.50 –0.25 30 Figure 49. Output Current and V SET Rev Page AD5755 +15V –15V 25° 300Ω LOAD TIME (µ +15V – ...
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... AD5755 OUT OUT OUT A 10 0mA TO 24mA RANGE 1kΩ LOAD 410kHz SW INDUCTOR = 10µH (XAL4040-103 –0.25 0 0.25 0.50 0.75 1.00 TIME (ms) Figure 50. Output Current Settling with DC-to-DC Converter vs. Time and Temperature (See Figure 80 OUT OUT ...
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... TO 24mA RANGE 1kΩ LOAD EXTERNAL R SET 410 kHz SW INDUCTOR = 10µH (XAL4040-103) 20 –40 – TEMPERATURE (°C) Figure 58. Output Efficiency vs. Temperature (See Figure 80) 0.6 0.5 0.4 0.3 0.2 0.1 0 –40 – TEMPERATURE (°C) Figure 59. Switch Resistance vs. Temperature AD5755-1 80 100 80 100 ...
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... Figure 63. REFOUT vs. Temperature (When the AD5755-1 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. ...
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... 25° /| 25° 0mA OUT Rev Page 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12 5.5V CC 12.6 –40 – TEMPERATURE (°C) Figure 69. Internal Oscillator Frequency vs. Temperature 14.4 14.2 14.0 13.8 13.6 13 25°C A 13.0 2.5 3.0 3.5 4.0 4.5 VOLTAGE (V) Figure 70. Internal Oscillator Frequency vs AD5755-1 80 100 5.0 5.5 Supply Voltage ...
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... V/μs. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5755-1 is powered-on specified as the area of the glitch in nV-sec. See Figure 29 and Figure 47. Digital-to-Analog Glitch Impulse ...
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... Efficiency at V BOOST_x × OUT BOOST _ x × This is defined as the power delivered to a channel’s V supply vs. the power delivered to the channel’s dc-to-dc input. The V quiescent current is considered part of the dc-to- BOOST_x dc converter’s losses. Rev Page AD5755-1 BOOST_x ...
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... Without the compensation capacitor capacitive loads can be driven. See Table 5 for information on connecting compensation capacitors. Reference Buffers The AD5755-1 can operate with either an external or internal reference. The reference input requires reference for specified performance. This input voltage is then buffered before it is applied to the DAC. ...
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... LDAC low after SYNC is taken high. Figure 74. Simplified Serial Interface of Input Loading Circuitry TRANSFER FUNCTION Table 6 shows the input code to ideal output voltage relationship for the AD5755-1 for straight binary data coding of the ±10 V output range. Table 6. Ideal Output Voltage to Input Code Relationship Figure 3 ...
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... Description Data DAC Data Register (×4) Used to write a DAC code to each DAC channel. AD5755-1 data bits = D15 to D0. There are four DAC data registers, one per DAC channel. Gain Register (×4) Used to program gain trim per channel basis. AD5755-1 data bits = D15 to D0. There are four gain registers, one per DAC channel. Offset Register (× ...
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... DC_DC BIT AND THE INT_ENABLE BIT SET. STEP 3: WRITE VALUE TO THE DAC DATA REGISTER. STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT. Figure 76. Steps for Changing the Output Range Rev Page AD5755-1 ...
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... DUT_AD0 Table 9. Input Register Decode Bit Description R/W Indicates a read from or a write to the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being addressed by the system controller. DUT_AD1 DREG2, DREG1, DREG0 Selects whether a data register or a control register is written to ...
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... DAC_AD1 DAC_AD0 D15 to D0 DAC channel address Offset adjustment OF3 OF2 … … … … DAC_AD1 DAC_AD0 DAC channel address AD5755 … … OF1 OF0 … … … ...
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... AD5755-1 CONTROL REGISTERS When writing to a control register, the format shown in Table 16 must be used. See Table 9 for information on the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits to the appropriate decode address for that register, according to Table 17 ...
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... voltage range (default voltage range. 0 ±5 V voltage range. 1 ±10 V voltage range current range current range current range. Rev Page OUTEN RSET DC_DC OVRNG AD5755 ...
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... D11, in the status register also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC ). Table 22. Programming the Software Register ...
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... To read back the gain register of Device 1, Channel A on the AD5755-1, implement the following sequence: 1. Write 0xA80000 to the AD5755-1 input register. This configures the AD5755-1 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don’t cares. 2. ...
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... Ramp Active This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). Over TEMP This bit is set if the AD5755-1 core temperature exceeds approximately 150°C. V Fault This bit is set if a fault is detected on the V ...
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... M is the code in the gain register (default code = the code in the offset register (default code = 2 STATUS READBACK DURING A WRITE The AD5755-1 has the ability to read back the status register contents during every write sequence. This feature is enabled via the STATREAD bit in the main control register. This allows the user to continuously monitor the status register and act quickly in the case of a fault ...
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... R stability of the output current over temperature, an external 15 kΩ low drift resistor can be connected to the R AD5755 used instead of the internal resistor, R1. The external resistor is selected via the DAC control register (see Table 20). Table 1 outlines the performance specifications of the AD5755-1 ...
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... HART. DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5755-1 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load ...
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... DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step 4 5 drive the AD5755-1 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous ...
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... The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5755-1, a low ESR tantalum or ceramic capacitor of 10 μF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature ...
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... AD5755-1 Reducing AI Current Requirements CC There are two main methods that can be used to reduce the AI current requirements. One method is to add an external CC compensation resistor, and the other is to use slew rate control. Both of these methods can be used in conjunction. A compensation resistor can be placed at the COMP in series with the 10 nF compensation capacitor kΩ ...
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... APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL When using a channel of the AD5755-1, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time ...
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... Traces The power supply lines of the AD5755-1 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs ...
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... Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5755-1 makes it ideal for isolated interfaces because the number of interface lines is kept , close to AV and to a minimum ...
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... INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Resolution (Bits) AD5755-1ACPZ 16 AD5755-1ACPZ-REEL7 16 EVAL-AD5755-1SDZ RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX 48 0.50 8.75 BSC BSC SQ 0.50 0.40 33 0.30 0.80 MAX ...