AD5755-1_11 AD [Analog Devices], AD5755-1_11 Datasheet - Page 38

• Manufacturer Part Number: AD5755-1_11
• Description: Quad Channel, 16-Bit,Serial Input, 4 mA to 20 mA and Voltage Output DAC,Dynamic Power Control
• Manufacturer: AD [Analog Devices]

AD5755-1
Status Register
The status register is a read only register. This register contains
any fault information as a well as a ramp active bit and a user
toggle bit. When the STATREAD bit in the main control
register is set, the status register contents can be read back on
Table 29. Decoding the Status Register
MSB
D15
DC-
DCD
Table 30. Status Register Options
Bit
DC-DCD
DC-DCC
DC-DCB
DC-DCA
User Toggle
PEC Error
Ramp Active
Over TEMP
V
V
V
V
I
I
I
I
OUT_D
OUT_C
OUT_B
OUT_A
OUT_D
OUT_C
OUT_B
OUT_A
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
D14
DC-
DCC
D13
DC-
DCB
Description
When this bit is set, it does not result in the FAULT pin going high.
When this bit is set, it does not result in the FAULT pin going high.
When this bit is set, it does not result in the FAULT pin going high.
When this bit is set, it does not result in the FAULT pin going high.
User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if needed.
Denotes a PEC error on the last data-word received over the SPI interface.
This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel).
This bit is set if the AD5755-1 core temperature exceeds approximately 150°C.
This bit is set if a fault is detected on the V
This bit is set if a fault is detected on the V
This bit is set if a fault is detected on the V
This bit is set if a fault is detected on the V
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
In current output mode, this bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be
reaching its V
for more information on this bit’s operation under this condition.
In voltage output mode, this bit is set if, on Channel D, the dc-to-dc converter is unable to regulate to 15 V as expected.
In current output mode, this bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be
reaching its V
more information on this bit’s operation under this condition.
In voltage output mode, this bit is set if, on Channel C, the dc-to-dc converter is unable to regulate to 15 V as expected.
In current output mode, this bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be
reaching its V
more information on this bit’s operation under this condition.
In voltage output mode, this bit is set if, on Channel B, the dc-to-dc converter is unable to regulate to 15 V as expected.
In current output mode, this bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be
reaching its V
more information on this bit’s operation under this condition.
In voltage output mode, this bit is set if, on Channel A, the dc-to-dc converter is unable to regulate to 15 V as expected.
D12
DC-
DCA
MAX
MAX
MAX
MAX
D11
User
toggle
voltage). In this case, the I
voltage). In this case, the I
voltage). In this case, the I
voltage). In this case, the I
D10
PEC
error
D9
Ramp
active
OUT_D
OUT_C
OUT_B
OUT_A
OUT_D
OUT_C
OUT_B
OUT_A
OUT_D
OUT_C
OUT_B
OUT_A
D8
Over
TEMP
Rev. A | Page 38 of 48
pin.
pin.
pin.
pin.
pin.
pin.
pin.
pin.
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
D7
V
fault
OUT_D
the SDO pin during every write sequence. Alternatively, if the
STATREAD bit is not set, the status register can be read using
the normal readback operation.
D6
V
fault
OUT_C
D5
V
fault
OUT_B
D4
V
fault
OUT_A
D3
I
fault
OUT_D
MAX
MAX
MAX
MAX
Functionality section for
Functionality section for
Functionality section for
Functionality section
D2
I
fault
OUT_C
D1
I
fault
OUT_B
LSB
D0
I
fault
OUT_A