UDA1345 PHILIPS [NXP Semiconductors], UDA1345 Datasheet - Page 7

• Manufacturer Part Number: UDA1345
• Description: Economy audio CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The UDA1345TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clocks (being the system clock itself
and the digital audio interface signals).
The system clock must be locked in frequency to the audio
digital interface input signals.
The BCK clock can be up to 128f
BCK frequency is 128 times the Word Select (WS)
frequency or less: f
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital I/O
data interface.
Note: the sampling frequency range is from 5 to 100 kHz,
however for the 512f
from 5 to 55 kHz.
2000 Apr 18
handbook, halfpage
Economy audio CODEC
V DDA(ADC)
V SSA(ADC)
SYSCLK
V ADCN
V ADCP
V ref(A)
V DDD
V SSD
VINR
VINL
MC1
MP1
MP2
MP3
Fig.2 Pin configuration.
BCK
10
11
12
13
14
1
2
3
4
5
6
7
8
9
s
clock mode the sampling range is
= < 128
UDA1345TS
MGS876
s
f
, or in other words the
WS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
.
V ref(D)
V SSO
VOUTL
V DDO
VOUTR
V DDA(DAC)
V SSA(DAC)
MC2
MP5
DATAI
DATAO
WS
BCK
MP4
7
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1345TS consists of two
5th-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 64.
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block (the pin to select this mode is given in
Section “L3 microcontroller mode”). This block can be
used in applications in which both 1 V (RMS) and
2 V (RMS) input signals can be input to the UDA1345TS.
In applications in which a 2 V (RMS) input signal is used,
a 12 k resistor must be used in series with the input of the
ADC. This forms a voltage divider together with the internal
ADC resistor and ensures that only 1 V (RMS) maximum
is input to the IC. Using this application for a 2 V (RMS)
input signal, the switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1; the power supply
voltage is assumed to be 3 V.
Table 1 Application modes using input gain stage
Decimation filter (ADC)
The decimation from 64f
The first stage realizes a 4th-order
This filter decreases the sample rate by 8. The second
stage consists of 2 half-band filters and a recursive filter,
each decimating by a factor of 2.
Present
Present
Absent
Absent
RESISTOR
(12 k )
INPUT GAIN
s
SWITCH
to 1f
0 dB
6 dB
0 dB
6 dB
s
is performed in two stages.
Preliminary specification
sin x
----------- -
UDA1345TS
x
characteristic.
0.5 V (RMS)
MAXIMUM
2 V (RMS)
1 V (RMS)
1 V (RMS)
VOLTAGE
INPUT