TLV320AIC3105_08 BURR-BROWN [Burr-Brown Corporation], TLV320AIC3105_08 Datasheet - Page 29

• Manufacturer Part Number: TLV320AIC3105_08
• Description: LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

STEREO AUDIO ADC
The TLV320AIC3105 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from
8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in
operation, the device requires that an audio master clock be provided and appropriate audio clock generation be
set up within the device.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully powered
or entirely powered down.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 f
output response with a group delay of 17/f
scales with the sample rate (f
f
can be independently set.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3105 integrates a second-order
analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC
power-down flag is no longer set, the audio master clock can be shut down.
STEREO AUDIO ADC HIGH-PASS FILTER
Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The
TLV320AIC3105 has a programmable first-order high-pass filter which can be used for this purpose. The digital
filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0,
N1, and D1. The transfer function of the digital high-pass filter is of the form:
48
f
MCLK (MHz)
2.048
3.072
4.096
6.144
8.192
12
13
16
19.2
19.68
48
S
S(ref)
. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that
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= 48 kHz
4
P
1
1
1
1
1
1
1
1
1
1
4
S
to the final output sampling rate of f
S
). The filter has minimum 75-dB attenuation over the stop band from 0.55 f
R
1
1
1
1
1
1
1
1
1
1
1
1
S
OVERVIEW (continued)
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. The –3-dB bandwidth of the decimation filter extends to 0.45 f
48
32
24
16
12
J
7
8
7
6
5
4
8
S
5264
1920
5618
1440
1200
9951
1920
. The decimation filter provides a linear phase
D
0
0
0
0
0
SLAS513A – FEBRUARY 2007 – REVISED JULY 2007
ACHIEVED f
47,999.71
47,999.79
44,100
48,000
48,000
48,000
48,000
48,000
48,000
48,000
48,000
48,000
S(ref)
TLV320AIC3105
% ERROR
–0.0006
–0.0004
0
0
0
0
0
0
0
0
0
0
S
S
to 64
and
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