PCA9541ABS/01 NXP [NXP Semiconductors], PCA9541ABS/01 Datasheet

PCA9541ABS/01

Manufacturer Part Number

PCA9541ABS/01

Description

2-to-1 I2C-bus master selector with interrupt logic and reset

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.PCA9541ABS01.pdf (41 pages)

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1. General description

The PCA9541A is a 2-to-1 I

master I

fails or the controller card is removed for maintenance. The two masters (for example,

primary and back-up) are located on separate I

downstream I

and are used to select one master at a time. Either master at any time can gain control of

the slave devices if the other master is disabled or removed from the system. The failed

master is isolated from the system and will not affect communication between the on-line

master and the slave devices on the downstream I

Two versions are offered for different architectures. PCA9541A/01 with channel 0 selected

at start-up, and PCA9541A/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which master has control of the

bus. One interrupt input (INT_IN) collects downstream information and propagates it to

the 2 upstream I

the previous bus master know that it is not in control of the bus anymore and to indicate

the completion of the bus recovery/initialization sequence. Those interrupts can be

disabled and will not generate an interrupt if the masking option is set.

A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a

STOP condition in order to set the downstream I

before actually switching the channel to the selected master.

An interrupt is sent to the upstream channel when the recovery/initialization procedure is

completed.

An internal bus sensor senses the downstream I

if a channel switch occurs during a non-idle bus condition. This function is enabled when

the PCA9541A recovery/initialization is not used. The interrupt signal informs the master

that an external I

and an interrupt will not be generated.

The pass gates of the switches are constructed such that the V

the maximum high voltage, which will be passed by the PCA9541A. This allows the use of

different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate

with 5 V devices without any additional protection.

The PCA9541A does not isolate the capacitive loading on either side of the device, so the

designer must take into account all trace and device capacitances on both sides of the

device, and pull-up resistors must be used on all channels.

External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O

pins are 6.0 V tolerant.

PCA9541A

2-to-1 I

Rev. 03 — 16 July 2009

C-bus applications where system operation is required, even when one master

C-bus master selector with interrupt logic and reset

C-bus slave devices. I

C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let

C-bus recovery/initialization needs to be performed. It can be disabled

C-bus master selector designed for high reliability dual

C-bus commands are sent by either I

C-buses that connect to the same

C-bus devices to an initialized state

C-bus trafﬁc and generates an interrupt

C-bus.

pin can be used to limit

Product data sheet

C-bus master

Related parts for PCA9541ABS/01

PCA9541ABS/01 Summary of contents

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PCA9541A 2-to-1 I Rev. 03 — 16 July 2009 1. General description The PCA9541A is a 2-to-1 I master I fails or the controller card is removed for maintenance. The two masters (for example, primary and back-up) are located on ...

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NXP Semiconductors An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin LOW resets the I does the internal Power-On Reset (POR) function. 2. Features I 2-to-1 bidirectional master selector C-bus interface ...

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... HVQFN16 PCA9541AD/03 SO16 PCA9541APW/03 TSSOP16 PCA9541ABS/03 HVQFN16 5. Marking Table 2. Type number PCA9541AD/01 PCA9541APW/01 PCA9541ABS/01 PCA9541AD/03 PCA9541APW/03 PCA9541ABS/03 PCA9541A_3 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thermal enhanced very thin quad ﬂ ...

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NXP Semiconductors 6. Block diagram PCA9541A SCL_MST0 SDA_MST0 RESET POWER-ON RESET V DD SCL_MST1 SDA_MST1 INT0 INT1 Fig 1. Block diagram of PCA9541A PCA9541A_3 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic ...

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... SDA_SLAVE SDA_MST0 13 SCL_SLAVE SCL_MST0 12 A3 RESET 11 A2 SCL_MST1 SDA_MST1 Fig 3. terminal 1 index area 1 12 SCL_MST0 RESET 2 11 PCA9541ABS/01 PCA9541ABS/ SCL_MST1 4 9 SDA_MST1 Transparent top view Rev. 03 — 16 July 2009 PCA9541A 1 16 INT0 PCA9541APW/01 PCA9541APW/ ...

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NXP Semiconductors 7.2 Pin description Table 3. Symbol INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 SCL_SLAVE SDA_SLAVE INT_IN V DD [1] HVQFN16 package die supply ground is connected to both the ...

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NXP Semiconductors 8. Functional description Refer to 8.1 Device address Following a START condition, the upstream master that wants to control the I make a status check must send the address of the slave it is accessing. The slave address ...

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NXP Semiconductors • During a write operation, the PCA9541A will acknowledge bytes sent to the IE and CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since read-only register. The 2 LSBs ...

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NXP Semiconductors • master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that longer connected ...

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NXP Semiconductors The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to be activated for a ‘functional interrupt test’. Remark: The regular way to proceed is that a master asks to take the control of ...

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NXP Semiconductors Table 6. Register 0 - Interrupt Enable (IE) register bit description Legend: * default value Bit Symbol Access Value 1 BUSINITMSK R/W 0 INTINMSK R/W [1] Default values are the same for PCA9541A/01, PCA9541A/03. 8.3.2 Register 1: Control ...

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NXP Semiconductors Table master reads its Control Register NMYBUS [1] MYBUS and NMYBUS is an exclusive-OR type function where: Equal values (00b or 11b) means that the master reading its Control Register has ...

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NXP Semiconductors Table 11. Default Control Register values Type version Master Bit 7 NTESTON TESTON PCA9541A/01 MST_0 0 MST_1 0 PCA9541A/03 MST_0 0 MST_1 0 Table 12 master device wants to take control of the I function of the current ...

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Table 12. Bus control sequence Read Control Register performed by the master Byte Status NBUSON BUSON NMYBUS MYBUS Byte [1] read Hex 0 bus off has control bus off no control bus off no ...

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NXP Semiconductors 8.4 Interrupt Status registers The PCA9541A provides 4 different types of interrupt: • To indicate to the former I • To indicate to the new I – The bus recovery/initialization has been performed and that the downstream channel ...

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NXP Semiconductors 8.4.3 Downstream interrupt An interrupt can also be generated by a downstream device by asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to ‘1’ by either master, INT0 ...

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NXP Semiconductors Table 14. Register 2 - Interrupt Status (ISTAT) register bit description Legend: * default value Bit Symbol Access Value [4] 2 BUSOK R only [4] 1 BUSINIT R only [2] 0 INTIN R only [1] Default values are ...

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NXP Semiconductors 8.6 External reset A reset can be accomplished by holding the RESET pin LOW for a minimum of t PCA9541A registers and I RESET input is once again HIGH. This input typically requires a pull-up resistor to V ...

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NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

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NXP Semiconductors 9.3 System conﬁguration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ ...

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NXP Semiconductors 9.5 Bus transactions slave address START condition R/W acknowledge from slave Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit Remark ...

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SDA_MST0 slave address command code register START condition R/W auto increment acknowledge from slave SCL_MST0 INT1 SCL_SLAVE SDA_SLAVE INT0 MASTER 1 ...

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NXP Semiconductors (1) SDA_MST0 slave address START condition R/W acknowledge from slave SCL_MST0 INT1 INT0 MASTER 1 has control of the bus ...

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NXP Semiconductors 10. Application design-in information 3.3 V 3.3 V Fig 17. Typical application 10.1 Speciﬁc applications The PCA9541A is a 2-to-1 I reliability I required even if one master fails or its controller card is removed for maintenance. The ...

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NXP Semiconductors 10.2 High reliability systems In a typical multipoint application, shown in primary and back-up) are located on separate I downstream I applications to provide high reliability of the I Fig 18. High reliability backplane application 2 I C-bus ...

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NXP Semiconductors 10.3 Masters with shared resources Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541A can be used to separate the masters, as shown in ...

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NXP Semiconductors Fig 21. Gatekeeper multiplexer application 10.5 Bus initialization/recovery to initialize slaves without hardware reset 2 If the I C-bus is hung, I and Slave 2 in PCA9541A/03 disconnects the bus when it is reset via the hardware reset ...

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NXP Semiconductors 11. Limiting values Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol tot T stg T ...

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NXP Semiconductors Table 16. Static characteristics Symbol Parameter Select inputs A0 to A3, INT_IN, RESET V LOW-level input voltage IL V HIGH-level input voltage IH I ...

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NXP Semiconductors 13. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL f SCL clock frequency SCL(init/rec) (bus initialization/bus recovery) t bus free time between a STOP and BUF START condition t ...

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NXP Semiconductors [ total capacitance of one bus line in pF. b [5] Measurements taken with 1 k pull-up resistor and 50 pF load. [6] Resetting the device while actively communicating on the bus may cause glitches or ...

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NXP Semiconductors START SCL SDA RESET 50 % INTn Fig 25. Deﬁnition of RESET timing 14. Test information Fig 26. Test circuitry for switching times PCA9541A_3 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset ...

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NXP Semiconductors 15. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

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NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

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NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the ...

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NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow soldering description” . 16.1 Introduction ...

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NXP Semiconductors 16.4 Reﬂow soldering Key characteristics in reﬂow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

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NXP Semiconductors Fig 30. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 17. Abbreviations Table 20. Acronym AI CDM DUT EEPROM ESD FRU HBM ...

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NXP Semiconductors 18. Revision history Table 21. Revision history Document ID Release date PCA9541A_3 20090716 • Modiﬁcations: Section 1 “General • Section 12 “Static and (old) Table 17 “Static characteristics” (V PCA9541A_2 20090604 PCA9541A_1 20090528 PCA9541A_3 Product data sheet 2 ...

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NXP Semiconductors 19. Legal information 19.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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