TDA9910HW/6 PHILIPS [NXP Semiconductors], TDA9910HW/6 Datasheet - Page 9

• Manufacturer Part Number: TDA9910HW/6
• Description: 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 5:
V
to +85 C; V
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
9397 750 14418
Objective data sheet
Symbol Parameter
SFDR
ACPR
d2
d3
CCA
CCA
(IM2)
(IM3)
D = guaranteed by design;
C = guaranteed by characterization;
I = 100 % industrially tested.
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with V
b) PECL mode 2: (DC levels vary 1:1 with V
c) PECL mode 3: (DC levels vary 1:1 with V
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to V
Output data acquisition: the output data is available after the maximum delay of t
The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
The total harmonic distortion is obtained with the addition of the first five harmonics.
The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
= 4.75 V to 5.25 V; V
= V
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
In that case CLKN pin has to be connected to the ground.
CCD
spurious free dynamic
range TDA9910/6
spurious free dynamic
range TDA9910/8
adjacent channel power
rejection
second order
intermodulation
distortion
third order
intermodulation
distortion
Characteristics
IN(p-p)
= 5 V, V
V
[8]
[8]
INN(p-p)
CCO
= 3.3 V, T
CCD
= 2.0 V
…continued
= 4.75 V to 5.25 V; V
amb
Conditions
f
f
f
f
f
f
f
channel spacing;
B = 4.096 MHz
f
channel spacing;
B = 4.096 MHz
f
f
f
f
f
f
f
f
f
f
f
f
0.5 dB; V
i
i
i
i
i
i
i
i
i1
i2
i1
i2
i1
i2
i1
i2
i1
i2
i1
i2
= 25 C and C
= 21.4 MHz
= 93 MHz
= 175 MHz
= 21.4 MHz
= 93 MHz
= 175 MHz
= 93 MHz; 5 MHz
= 175 MHz; 5 MHz
= 21 MHz;
= 22 MHz
= 93 MHz;
= 96 MHz
= 174 MHz;
= 176 MHz
= 21 MHz;
= 22 MHz
= 93 MHz;
= 96 MHz
= 174 MHz;
= 176 MHz
CCD
CCD
CCD
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
) CLK and CLKN inputs are at differential PECL levels.
FSIN
Rev. 02 — 9 December 2004
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
CCO
= V
L
= 10 pF; unless otherwise specified.
CCA1
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
Test
1.77 V; V
[1]
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
i(CM)
d(o)
= V
.
CCA1
Typ
76
73
73
79
75
72
86
74
81
83
80
87
88
83
1.85 V; typical values measured at
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TDA9910
amb
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
= 40 C
CCA.
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