TDA9984AHW NXP [NXP Semiconductors], TDA9984AHW Datasheet
TDA9984AHW
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TDA9984AHW Summary of contents
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TDA9984A HDMI 1.3 transmitter with 1080p upscaler embedded Rev. 04 — 15 January 2009 1. General description The TDA9984A is a High-Definition Multimedia Interface (HDMI) v. 1.3 transmitter with embedded 1080p upscaling functionality backward compatible DVI 1.0 and ...
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NXP Semiconductors I Programmable color space converter allows to input RGB video data and to output RGB or YCbCr HDMI video data input YCbCr video data and to output RGB or YCbCr 4 ...
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... Input 1080p, YCbCr embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr kHz S/PDIF. 5. Ordering information Table 2. Type number Package TDA9984AHW HTQFP80 [1] A lead-free package is required to comply with the new legislation. TDA9984A_4 Product data sheet HDMI 1.3 transmitter with 1080p upscaler embedded = 0 V ...
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... SSH SSA(FRO)(3V3) SSA(PLL)(3V3) SSA(PLL)(1V8) DDC_SDA DDC_SCL DDC BUS INTERRUPT 17 MASTER INT GENERATION HPD 18 HPD MANAGEMENT RxSENSE 27 TXC+ OTP 26 MEMORY TXC KEYS 30 TX0+ 29 TX0 HDCP TMDS PROCESSING SERIALIZER 33 TX1+ 32 TX1 36 TX2+ 35 TX2 24 EXT_SWING TDA9984AHW 001aag595 ...
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... Table 3. Symbol HSYNC/HREF VSYNC/VREF V PP AP7 AP6 AP5 AP4 AP3 TDA9984A_4 Product data sheet HDMI 1.3 transmitter with 1080p upscaler embedded TDA9984AHW Pin description [1] Pin Type Description 1 I horizontal synchronization or reference input 2 I vertical synchronization or reference input 3 P programming voltage for OTP memory; connect to ...
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NXP Semiconductors Table 3. Symbol AP2 AP1 AP0 ACLK V DDD(3V3) V SSD V SSA(PLL)(1V8) V DDA(PLL)(1V8) INT HPD DDC_SDA DDC_SCL TM V SSA(FRO)(3V3) V DDA(FRO)(3V3) EXT_SWING V SSH TXC TXC+ V DDH(3V3) TX0 TX0+ V SSH TX1 TX1+ V ...
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NXP Semiconductors Table 3. Symbol V DDD(3V3) VPC[7] VPC[6] VPC[5] VPC[4] VPC[3] VPC[2] VPC[1] VPC[0] VPB[7] VPB[6] V DDC(1V8) V SSC VPB[5] VPB[4] VPB[3] VPB[2] VPB[1] VCLK VPB[0] VPA[7] VPA[6] VPA[5] V DDD(3V3) V SSD V SSC V DDC(1V8) VPA[4] ...
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NXP Semiconductors 8. Functional description The TDA9984A is designed to convert digital data (video and audio) provided by a Set-Top Box or DVD into an HDMI output, which could be used in TV with HDMI or DVI input. The TDA9984A ...
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NXP Semiconductors The device can swap and invert (in case of a little endian stream) the incoming video data via the I to match the expectation of the video processing block; see When input ports are not used ...
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Table 5. Inputs of video input formatter Space color Format Channels Sync RGB 8-bit external embedded YCbCr 8-bit external embedded YCbCr ...
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NXP Semiconductors 8.1.2.1 RGB external sync input (rising edge) Table 6. RGB mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin ...
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NXP Semiconductors 8.1.2.2 YCbCr external sync input (rising edge) Table 7. YCbCr mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin ...
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NXP Semiconductors 8.1.2.3 YCbCr ITU656-like external sync input (rising edge) Table 8. YCbCr ITU656-like rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A ...
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NXP Semiconductors 8.1.2.4 YCbCr ITU656-like external sync input (rising and falling) Table 9. YCbCr ITU656-like double edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port ...
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NXP Semiconductors 8.1.2.5 YCbCr ITU656-like embedded sync input (rising edge) Table 10. YCbCr ITU656-like embedded rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port ...
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NXP Semiconductors 8.1.2.6 YCbCr ITU656-like embedded sync input (rising and falling) Table 11. YCbCr ITU656-like embedded double edge mappings Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video ...
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NXP Semiconductors 8.1.2.7 YCbCr semi-planar external input (rising edge) Table 12. YCbCr semi-planar rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video ...
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NXP Semiconductors 8.1.2.8 YCbCr semi-planar embedded sync input (rising edge) Table 13. YCbCr semi-planar embedded rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port ...
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NXP Semiconductors 8.1.3 Synchronization The TDA9984A can be synchronized with external input signals HSYNC and VSYNC or with extraction of the sync information from embedded sync codes (SAV/EAV) inside the video. 8.1.3.1 Timing extraction generator This block can extract the ...
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NXP Semiconductors • Maximum output operating frequency is 148.5 MHz; HDTV supported 1080p both PAL and NTSC • Input video standards YCbCr semi-planar and ITU656 (no RGB, nor YCbCr 8.1.5.2 ...
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NXP Semiconductors 8.1.7 Color space converter The color-space converter is used to convert input video data from one type to another color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each coefficient is ...
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NXP Semiconductors The TDA9984A is able to recover the original clock from the S/PDIF signal (no need of external clock). In addition, it can also use an external clock to decode the S/PDIF signal. 2 8.2.2 I S-bus There are ...
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NXP Semiconductors If the input clock has a frequency of 32f input clock has a frequency of 64f truncated to 24-bit format and padded with zeros. If the input clock has a frequency of 64f and is right justified, audio ...
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NXP Semiconductors Fig 14. Receiver sensitivity detection As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set to logic 1 (see register INT_FLAGS_3, page 00h, address 12h). As soon as the cable is ...
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NXP Semiconductors V o(se) (mV) (1) Swing character data (2) Upper limit (600 mV) (3) Lower limit (400 mV) Fig 15. TMDS single-ended output swing as a function of external resistor R 8.4.3 Pixel repetition To transmit video formats with ...
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NXP Semiconductors Here is described briefly the clock system architecture: • PLL double edge: generates a clock at twice the VCLK input frequency to capture correctly the data at the video formatter input • PLL scaling: creates a new video ...
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NXP Semiconductors 8.5.5 Power management The TDA9984A can be powered down via the I switched off and the biasing structure of the output stage is disconnected (all activity is reduced). Therefore, the TDA9984A has a very low power consumption which ...
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NXP Semiconductors 2 8.7 I C-bus interface 2 The I C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant. Pin I2C_SCL is only an input pin. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The registers of the ...
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... NXP Semiconductors • TDA9984AHW will have the value 1000 XXXX The four LSBs are used for indicating the die version. 10. Limiting values Table 20. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD(3V3) V DD(1V8 stg T amb esd 11 ...
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NXP Semiconductors Table 22. Supplies …continued DD(3V3) DD(1V8) Typical values are measured at T Symbol Parameter P power consumption cons P total power dissipation tot P power dissipation in power-down pd ...
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NXP Semiconductors 13. Dynamic characteristics Table 25. Timing characteristics DD(3V3) DD(1V8) otherwise specified. Symbol Parameter Video inputs; see Figure 17 f maximum clock frequency clk(max) clock duty cycle clk t data ...
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NXP Semiconductors DE, HSYNC, VSYNC a. Sync on rising edge DE, HSYNC, VSYNC b. Sync on falling edge DE, HSYNC, VSYNC c. Sync on rising and falling (double) edge Fig 17. Set-up and hold time for various clock modes 13.1 ...
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NXP Semiconductors Table 26. Input format …continued Input pins Signal RGB Video port B VPB[0] Y[0]/G[0] G[0] VPB[1] Y[1]/G[1] G[1] VPB[2] Y[2]/G[2] G[2] VPB[3] Y[3]/G[3] G[3] VPB[4] Y[4]/G[4] G[4] VPB[5] Y[5]/G[5] G[5] VPB[6] Y[6]/G[6] G[6] ...
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NXP Semiconductors 13.2 Timing parameters for supported video The TDA9984A supports all EIA/CEA-861B standards and ATSC video input formats. Table 27. Timing parameters for EIA/CEA-861B Format Format V frequency (Hz) 59.94 Hz systems 1 (VGA) 640 480p 59.9401 2, 3 ...
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NXP Semiconductors Table 27. Timing parameters for EIA/CEA-861B Format Format V frequency (Hz) 27, 28 720 288p 50.000 29, 30 1440 576p 50.000 31 1920 1080p 50.000 [1] The format can also be defined with a repetition factor of up ...
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NXP Semiconductors 14. Package outline HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body mm; exposed die pad y exposed die pad pin 1 index ...
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NXP Semiconductors 15. Abbreviations Table 30. Acronym ACR AV CMOS CTS CTS/N DDC DE DTS DTV DVD DVI EAV EDID E-EDID FREF HBR HD HDCP HDMI HDTV HREF HSYNC KSV LSB LV-TTL MSB NTSC OTP PAL PCM PLL SAV SHA-1 ...
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NXP Semiconductors 16. Revision history Table 31. Revision history Document ID Release date TDA9984A_4 20090115 • Modifications: All document: changed Y-C • Section • Section • Figure • Table • Section HBR • Section • Section • Table • Table ...
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NXP Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...