PCA9549PW NXP [NXP Semiconductors], PCA9549PW Datasheet

PCA9549PW

Manufacturer Part Number

PCA9549PW

Description

Octal bus switch with individually I2C-bus controlled enables

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.PCA9549PW.pdf (25 pages)

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1. General description

2. Features

The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled

by the I

with minimal propagation delay. Any individual A to B channel or combination of channels

can be selected via the I

Port A to Port B, or vice versa. When the I

creating a high-impedance state between the two ports, which stops the data ﬂow.

An active LOW reset input (RESET) allows the PCA9549 to recover from a situation

where the I

state machine and causes all the bits to be open, as does the internal power-on reset

function.

Three address pins allow up to eight devices on the same bus.

PCA9549

Octal bus switch with individually I

Rev. 02 — 13 July 2009

8-bit bus switch (CBT)

Active LOW RESET input

3 address pins allowing up to 8 devices on the I

Bit selection via I

Power-up with all bits deselected

Low R

No glitch on power-up

Supports hot insertion

Low standby current

Operating power supply voltage range of 2.3 V to 5.5 V

5 V tolerant inputs

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO24, TSSOP24, HVQFN24

C-bus interface logic; compatible with SMBus standards

switch connection between two ports

C-bus. The low ON-state resistance of the switch allows connections to be made

C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I

switches

C-bus bit is HIGH (logic 1), the switch is on and data can ﬂow from

C-bus, in any combination

C-bus, determined by the contents of the programmable Control

C-bus bit is LOW (logic 0), the switch is open,

C-bus

C-bus controlled enables

Product data sheet

C-bus

Related parts for PCA9549PW

PCA9549PW Summary of contents

Page 1

PCA9549 Octal bus switch with individually I Rev. 02 — 13 July 2009 1. General description The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled by the I with minimal propagation delay. Any individual ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Type number PCA9549D PCA9549PW PCA9549BS 3.1 Ordering options Table 2. Type number PCA9549D PCA9549PW PCA9549BS 4. Block diagram RESET SCL SDA Fig 1. PCA9549_2 Product data sheet Octal bus switch with individually I Ordering information ...

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... Transparent top view Pin conﬁguration of HVQFN24 (transparent top view) Rev. 02 — 13 July 2009 PCA9549 2 C-bus controlled enables RESET PCA9549PW Fig 3. Pin conﬁguration of TSSOP24 ...

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NXP Semiconductors 5.2 Pin description Table 3. Symbol A0 A1 RESET SCL SDA V DD [1] HVQFN24 package die supply ground ...

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NXP Semiconductors 6. Functional description 6.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9549 is shown in internal pull-up resistors are incorporated on the ...

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NXP Semiconductors Table 4. Write = channel selection; read = channel status [1] Several bits can be enabled at the same time. For example ...

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NXP Semiconductors (1) maximum. (2) typical. (3) minimum. Fig 7. Figure 7 PCA9549 is only tested at the points speciﬁed in order for the PCA9549 to act as a voltage translator, the V or lower than the lowest bus voltage. ...

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NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

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NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 10. System conﬁguration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed ...

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NXP Semiconductors 7.4 Bus transactions Data is transmitted to the PCA9549 control register using the Write mode as shown in Figure 12. SDA Fig 12. Write control register Data is read from the PCA9549 using the Read mode as shown ...

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NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C; unless otherwise speciﬁed. See SS amb Symbol Parameter Supply V supply voltage DD I supply current DD I ...

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NXP Semiconductors Table 7. Static characteristics +85 C; unless otherwise speciﬁed. See SS amb Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb ...

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NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t LOW ...

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NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 14. Deﬁnition of timing on the I SCL SDA RESET 50 % Fig 15. Deﬁnition of RESET timing PCA9549_2 Product data sheet Octal bus switch with individually ...

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NXP Semiconductors 11. Application information C-bus/SMBus MASTER Remark: B can also be input and A can also be output as shown in bit 8. Fig 16. Typical application Fig 17. Custom multiplexer or ...

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NXP Semiconductors Fig 18. 2 channel 4-to-1 multiplexer or demultiplexer 12. Test information Fig 19. Test circuit PCA9549_2 Product data sheet Octal bus switch with individually PULSE GENERATOR C = load capacitance includes jig ...

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NXP Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

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NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

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NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are ...

Page 20

NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow soldering description” . 14.1 Introduction ...

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NXP Semiconductors 14.4 Reﬂow soldering Key characteristics in reﬂow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 22

NXP Semiconductors Fig 23. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 15. Abbreviations Table 11. Acronym CBT CDM DUT ESD HBM 2 I ...

Page 23

NXP Semiconductors 16. Revision history Table 12. Revision history Document ID Release date PCA9549_2 20090713 • Modiﬁcations: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have ...

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NXP Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 25

NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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