SAA7183WP PHILIPS [NXP Semiconductors], SAA7183WP Datasheet - Page 32

• Manufacturer Part Number: SAA7183WP
• Description: Digital Video Encoder EURO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
1996 Jul 08
handbook, full pagewidth
handbook, full pagewidth
Digital Video Encoder (EURO-DENC)
RTCI
The data demultiplexing phase is coupled to the internal horizontal phase.
The C
The phase of the RCV2 signal is programmed to 0F2h (110h for 50 Hz) in this example in output mode (RCV2S).
(1) Sequence bit:
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
PAL = logic 0 then (R
NTSC = logic 0 then no change.
LLC
CREF
VP(n)
DP(n)
RCV2
ref
signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
H/L transition
count start
128
time slot:
Y) line normal; PAL = logic 1 then (R
LOW
0 1
Cb(0)
13
Y(0)
not used in SAA7182/83
increment
HPLL
14
0
Fig.15 Digital TV timing.
reserved
Cr(0)
4 bits
Y(1)
Fig.16 RTCI timing.
19
21
Y) line inverted.
32
Cb(2)
Y(2)
FSCPLL increment (4)
sample
valid
sample
invalid
Cr(2)
Y(3)
SAA7182; SAA7183
reserved
8/LLC
5 bits
Preliminary specification
sequence
0
bit (1)
Cb(4)
Y(4)
MBE739
67 68
bit (1)
reset
reserved (2)
MGB700