EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 17

• Manufacturer Part Number: EP1C20F
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–8. Carry Select Chain
Altera Corporation
May 2008
LAB Carry-In
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
LAB Carry-Out
0
0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
1
1
Sum1
Sum2
Sum3
Sum4
Sum5
Sum6
Sum7
Sum8
Sum9
Sum10
Figure 2–8
One portion of the LUT generates the sum of two bits using the input
signals and the appropriate carry-in bit; the sum is routed to the output
of the LE. The register can be bypassed for simple adders or used for
accumulator functions. Another portion of the LUT generates carry-out
bits. A LAB-wide carry-in bit selects which chain is used for the addition
of given inputs. The carry-in signal for each chain, carry-in0 or
carry-in1, selects the carry-out to carry forward to the carry-in signal
of the next-higher-order bit. The final carry-out signal is routed to an LE,
where it is fed to local, row, or column interconnects.
shows the carry-select circuitry in a LAB for a 10-bit full adder.
LAB Carry-In
Carry-In0
Carry-In1
data1
data2
Carry-Out0
LUT
LUT
LUT
LUT
Carry-Out1
Logic Elements
Sum
Preliminary
2–11