EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 23
EP1C20F
Manufacturer Part Number
EP1C20F
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP1C20F.pdf
(106 pages)
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Altera Corporation
May 2008
LUT Chain
Register Chain
Local Interconnect
Direct Link
Interconnect
R4 Interconnect
C4 Interconnect
LE
M4K RAM Block
PLL
Column IOE
Row IOE
Table 2–2. Cyclone Device Routing Scheme
Source
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All embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects
to row and column interconnects and has local interconnect regions
driven by row and column interconnects. These blocks also have direct
link interconnects for fast connections to and from a neighboring LAB.
Table 2–2
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v
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shows the Cyclone device's routing scheme.
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Destination
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MultiTrack Interconnect
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Preliminary
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2–17
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