EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 85

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EP1C20F

Manufacturer Part Number
EP1C20F
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet

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Altera Corporation
May 2008
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
timing. All registers are within the IOE.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
M4KRC
M4KWC
M4KWERESU
M4KWEREH
M4KBESU
M4KBEH
M4KDATAASU
M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
M4KDATABH
M4KADDRBSU
M4KADDRBH
M4KDATACO1
M4KDATACO2
M4KCLKHL
M4KCLR
R4
C4
LOCAL
Table 4–27. M4K Block Internal Timing Microparameters
Table 4–28. Routing Delay Internal Timing Microparameters
Symbol
Symbol
Figure 4–2
shows the timing model for bidirectional IOE pin
1,234
Min
286
Min
72
43
72
43
72
43
72
43
72
43
72
43
-6
-6
4,379
2,910
4,351
Max
Max
621
261
338
244
1,562
Min
328
Min
82
49
82
49
82
49
82
49
82
49
82
49
-7
-7
5,035
3,346
5,003
Max
Max
714
300
388
281
1,818
Min
371
Min
93
55
93
55
93
55
93
55
93
55
93
55
-8
-8
Timing Model
5,691
3,783
5,656
Max
Max
807
339
439
318
Preliminary
Unit
Unit
4–15
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps

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