EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 56

• Manufacturer Part Number: EP1C20F
• Description: Cyclone FPGA Family
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
2–50
Preliminary
of the standard. Using minimum settings provides signal slew rate
control to reduce system noise and signal overshoot.
possible settings for the I/O standards with drive strength control.
Open-Drain Output
Cyclone devices provide an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write-enable signals) that can be asserted by any of several devices.
Notes to
(1)
(2)
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL (2.5 V)
LVTTL (1.8 V)
LVCMOS (1.5 V)
Table 2–11. Programmable Drive Strength
SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not
support programmable drive strength.
This is the default current strength setting in the Quartus II software.
Table
I/O Standard
2–11:
I
OH
/I
OL
Note (1)
Current Strength Setting (mA)
Table 2–11
24(2)
12(2)
16(2)
12(2)
8(2)
12
16
12
4
8
2
4
8
2
8
2
8
2
4
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May 2008