XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 35

no-image

XC2S100-5CS144I

Manufacturer Part Number
XC2S100-5CS144I
Description
Spartan-II FPGA Family
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
DS001-2 (v2.8) June 13, 2008
Product Specification
ADDR_A
ADDR_B
CLK_A
CLK_B
WE_A
WE_B
DO_A
DO_B
EN_A
EN_B
DI_A
DI_B
R
Figure 34: Timing Diagram for a True Dual-Port Read/Write Block RAM Memory
ADDR
DOUT
1111
00
RST
CLK
DIN
WE
EN
MEM (00)
DISABLED
AAAA
Figure 33: Timing Diagram for Single-Port Block RAM Memory
00
T
BCCS
1111
00
AAAA
T
T
T
T
BPWH
BACK
BDCK
BECK
DDDD
T
AAAA
00
BCKO
READ
T
BWCK
MEM (00)
9999
7E
VIOLATION
1111
T
7E
BCCS
www.xilinx.com
9999
9999
CCCC
0F
WRITE
BBBB
CCCC
AAAA
0F
T
0F
BPWL
BBBB
Spartan-II FPGA Family: Functional Description
AAAA
BBBB
7E
1111
0F
READ
MEM (7E)
UNKNOWN
0000
0F
T
BCCS
UNKNOWN
DS001_33_061200
DISABLED
2222
2222
7E
8F
2222
1111
7E
FFFF
DS001_34_061200
2222
1A
Module 2 of 4
FFFF
35

Related parts for XC2S100-5CS144I