XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 9

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V
be provided if the signaling standard requires one. The
provision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require V
and/or V
connected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see
multiple V
voltage. Voltage is determined by the output standards in
use.
Within a bank, output standards may be mixed only if they
use the same V
Table
their open-drain outputs do not depend on V
Table 4: Compatible Output Standards
Some input standards require a user-supplied threshold
voltage, V
DS001-2 (v2.8) June 13, 2008
Product Specification
V
3.3V
2.5V
1.5V
CCO
4. GTL and GTL+ appear under all voltages because
REF
CCO
REF
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
GTL, GTL+
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
R
voltages. These voltages are externally
. In this case, certain user-I/O pins are
Figure 3: Spartan-II I/O Banks
pins which must be connected to the same
CCO
Bank 0
Bank 5
. Compatible standards are shown in
GCLK3
GCLK1
Compatible Standards
Spartan-II
Device
Figure
GCLK2
GCLK0
3). Each bank has
Bank 1
Bank 4
REF
CCO
DS001_03_060100
voltage must
.
CCO
www.xilinx.com
automatically configured as inputs for the V
About one in six of the I/O pins in the bank assume this role.
V
consequently only one V
each bank. All V
connected to the external voltage source for correct
operation.
In a bank, inputs requiring V
that do not but only one V
bank. Input buffers that use V
LVTTL, LVCMOS2, and PCI are 5V tolerant. The V
V
Within a given package, the number of V
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
a superset of the V
possible to design a PCB that permits migration to a larger
device. All V
be connected to the V
Independent Banks Available
Configurable Logic Block
The basic building block of the Spartan-II FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. Output from the function
generator in each LC drives the CLB output and the D input
of the flip-flop. Each Spartan-II FPGA CLB contains four
LCs, organized in two similar slices; a single slice is shown
in
In addition to the four basic LCs, the Spartan-II FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-II FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit
synchronous RAM. Furthermore, the two LUTs within a
slice can be combined to create a 16 x 2-bit or 32 x 1-bit
synchronous RAM, or a 16 x 1-bit dual-port synchronous
RAM.
The Spartan-II FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in
applications such as Digital Signal Processing.
Independent Banks
REF
REF
Figure
pins within a bank are interconnected internally and
pins for each bank appear in the device pinout tables.
Package
Spartan-II FPGA Family: Functional Description
4.
REF
pins for the largest device anticipated must
REF
REF
pins in the bank, however, must be
REF
pins used for smaller devices, it is
REF
VQ100
PQ208
REF
REF
voltage, and not used for I/O.
1
REF
voltage can be used within
REF
voltage may be used within a
pins. Since these are always
can be mixed with those
are not 5V tolerant.
CS144
TQ144
REF
4
REF
and V
Module 2 of 4
voltage.
CCO
FG256
FG456
CCO
8
pins
and
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