XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 70

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

Table 36: Spartan-II Family Package Options
Note: Some early versions of Spartan-II devices, including
the XC2S15 and XC2S30 ES devices and the XC2S150
with date code 0045 or earlier, included a power-down pin.
For more information, see
VCCO Banks
Some of the I/O standards require specific V
These voltages are externally connected to device pins that
serve groups of IOBs, called banks. Eight I/O banks result
from separating each edge of the FPGA into two banks (see
Figure 3
which must be connected to the same voltage. In the
smaller packages, the V
banks, effectively reducing the number of independent
banks available (see
banks are shown in the Pinout Tables with V
multiple banks connected to the same pin.
Table 37: Independent VCCO Banks Available
Package Overview
Table 36
package styles for the Spartan-II family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “CS144” package becomes
“CSG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in
DS001-4 (v2.8) June 13, 2008
Product Specification
Notes:
1.
VQ100 / VQG100
TQ144 / TQG144
CS144 / CSG144
PQ208 / PQG208
FG256 / FGG256
FG456 / FGG456
Independent Banks
Package mass is ±10%.
Package
Package
in Module 2). Each bank has multiple V
shows the six low-cost, space-saving production
Table
R
38.
Leads
100
144
144
208
256
456
Table
CCO
VQ100
PQ208
Answer Record 10500
Very Thin Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
Chip Scale Ball Grid Array (CSBGA)
Plastic Quad Flat Pack (PQFP)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
37). These interconnected
1
pins are connected between
CS144
TQ144
4
Type
CCO
CCO
.
CCO
pads for
voltages.
FG256
FG456
pins
8
www.xilinx.com
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table
Material Declaration Data Sheets (MDDS) are also
available on the
Table 38: Xilinx Package Documentation
Maximum
VQ100
VQG100
TQ144
TQG144
CS144
CSG144
PQ208
PQG208
FG256
FGG256
FG456
FGG456
140
176
284
I/O
60
92
92
Package
38.
Lead Pitch
(mm)
0.5
1.0
0.5
0.8
0.5
1.0
Xilinx web site
Spartan-II FPGA Family: Pinout Tables
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Drawing
Area (mm)
30.6 x 30.6
Footprint
16 x 16
22 x 22
12 x 12
17 x 17
23 x 23
for each package.
PK173_VQ100
PK130_VQG100
PK169_TQ144
PK126_TQG144
PK149_CS144
PK103_CSG144
PK166_PQ208
PK123_PQG208
PK151_FG256
PK105_FGG256
PK154_FG456
PK109_FGG456
Height
(mm)
1.20
1.60
1.20
3.70
2.00
2.60
MDDS
Module 4 of 4
Mass
0.6
1.4
0.3
5.3
0.9
2.2
(g)
(1)
70