XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 54

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)
DS001-3 (v2.8) June 13, 2008
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
4.
Notes:
1.
2.
3.
CTT
AGP
Input/Output
Standard
V
Tested according to the relevant specifications.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
Methodology," page
DLL output jitter is already included in the timing calculation.
For data output with different standards, adjust delays with the values shown in
Standards," page
Global Clock Input Adjustments," page
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
Methodology," page
For data output with different standards, adjust delays with the values shown in
Standards," page
Global Clock Input Adjustments," page
T
OL
Symbol
Symbol
ICKOFDLL
T
ICKOF
and V
R
OH
for lower drive currents are sample tested.
V, Min
–0.5
–0.5
59. For a global clock input with standards other than LVTTL, adjust delays with values from the
59. For a global clock input with standards other than LVTTL, adjust delays with values from the
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, with DLL.
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, without DLL.
60.
60.
V
IL
V
V
REF
REF
V, Max
Description
Description
– 0.2
– 0.2
61.
61.
V
V
REF
REF
V, Min
+ 0.2
+ 0.2
www.xilinx.com
V
"Constants for Calculating TIOOP"
"Constants for Calculating TIOOP"
IH
Spartan-II FPGA Family: DC and Switching Characteristics
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
V, Max
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and
junction temperature). Values apply to all Spartan-II devices
unless otherwise noted.
3.6
3.6
Device
All
V
10% V
REF
V, Max
"IOB Output Delay Adjustments for Different
"IOB Output Delay Adjustments for Different
V
Min
All
OL
– 0.4
CCO
Min
All
Speed Grade
(1)
Speed Grade
V
90% V
and
and
REF
Max
V, Min
4.5
4.5
4.5
4.6
4.6
4.7
-6
V
(1)
Max
OH
2.9
"Delay Measurement
"Delay Measurement
-6
+ 0.4
CCO
Note (2)
Max
Max
5.4
5.4
5.4
5.5
5.5
5.6
3.3
-5
-5
mA
I
OL
8
"I/O Standard
"I/O Standard
Module 3 of 4
Note (2)
Units
Units
ns
mA
I
ns
ns
ns
ns
ns
ns
–8
OH
54