XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 113

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
Table 51: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
2. Output timing is measured at 50% V
3. DCM output jitter is already included in the timing calculation.
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA, Fast
Slew Rate, without DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page
Global Clock and OFF without DCM
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
R
Description
26.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
CC
threshold with test setup shown in
Symbol
T
ICKOF
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XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
Figure
6. For other I/O standards, see
3.19
3.39
3.59
3.62
3.62
3.73
3.89
4.00
4.38
4.38
N/A
-7
Speed Grade
3.52
3.91
4.00
4.08
4.08
4.12
4.28
4.43
4.87
4.87
5.32
-6
3.82
4.27
4.36
4.46
4.46
4.50
4.67
4.84
5.33
5.33
5.82
-5
Table
Module 3 of 4
37.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42