XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 128

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules:
•
•
DS083 (v4.7) November 5, 2007
Product Specification
09/15/05
10/10/05
03/05/07
11/05/07
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Introduction and Overview (Module 1)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Functional Description (Module 2)
Date
R
Version
4.4
4.5
4.6
4.7
•
•
•
•
•
•
•
•
•
No changes in Module 3 for this revision.
Updated copyright notice and legal disclaimer.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table
non-8B/10B-encoded data).
Table
-
-
Table
Table
-
-
Table
-
-
-
Table
respecified.
Table
Changed XC2VPX70 variable baud rate specification to fixed-rate operation at
4.25 Gb/s.
Table
-
-
Power dissipation for 10.3125 Gb/s deleted.
Max I
F
T
specifications for two bit rate ranges.
T
specification.
T
maximum specifications.
All parameters: Deleted specifications for 10.3125 Gb/s.
T
T
GCLK
GJTT
LOCK
PHASE
RJTOL
JTOL
2: Added Footnote (7) to AVCCAUXRX for RocketIO X (1.8V for all
3:
11: Added specification for minimum p-p differential input voltage.
22:
24:
26: Restructured table. Total Jitter parameter added. All jitter parameters
28: Restructured table and added new specifications.
15: Removed -7 designations for XC2VPX20 and XC2VPX70 devices.
CCAUXTX
, T
: Changed measurement units to picoseconds and added maximum
: Changed high end of range to 425 MHz.
: Changed measurement units to microseconds and adderd typical
: Added typical specifications.
: Changed measurement units to microseconds and adderd typical and
SJTOL
, and T
www.xilinx.com
and I
CCAUXRX
DDJTOL
•
•
: Added typical and maximum specifications.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC
and Switching Characteristics (Module 3)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Pinout Information (Module 4)
specifications added for Virtex-II Pro.
Revision
Module 3 of 4
(“CRITICAL
57