CY8C20111_11 CYPRESS [Cypress Semiconductor], CY8C20111_11 Datasheet

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CY8C20111_11

Manufacturer Part Number
CY8C20111_11
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1. Features
Cypress Semiconductor Corporation
Document Number: 001-53516 Rev. *G
Capacitive button input tied to a configurable output
Target Applications
Industry's best configurability
Advanced features
Wide range of operating voltages
Robust sensing algorithm
High sensitivity, low noise
Immunity to RF and AC noise
Low radiated EMC noise
Supports wide range of input capacitance, sensor shapes,
and sizes
Printers
Cellular handsets
LCD monitors
Portable DVD players
Custom sensor tuning
Output supports strong 20 mA sink current
Output state can be controlled through I
CapSense input state
Run time reconfigurable over I
Plug-and-play with factory defaults – tuned to support up to
1 mm overlay
Nonvolatile storage of custom settings
Easy integration into existing products – configure output to
match system
No external components required
World class free configuration tool
2.45 V to 2.9 V
3.10 V to 3.6 V
4.75 V to 5.25 V
2
C
2
C or directly from
CapSense
198 Champion Court
Two Button Capacitive Controllers
2. Overview
The CapSense
sensing (CapSense) buttons and two general purpose outputs in
CY8C20121 and one CapSense button and one general
purpose output in CY8C20111. The device functionality is
configured through the I
nonvolatile memory for automatic loading at power on. The
digital outputs are controlled from CapSense inputs in factory
default settings, but are user configurable for direct control
through I
The four key blocks that make up the CY8C20111 and
CY8C20121 controllers are: a robust capacitive sensing core
with high immunity against radiated and conductive noise,
control registers with nonvolatile storage, configurable outputs,
and I
parameters needed to adjust the operation and sensitivity of the
CapSense buttons and outputs and permanently store the
settings. The standard I
the host to configure the device and read sensor information in
real time. I
hardware strapping.
®
I
Industrial temperature range: –40 °C to +85 °C
Available in 8-Pin SOIC package
2
C communication
Supported from 1.8 V
Internal pull-up resistor support option
Data rate up to 400 kbps.
Configurable I
Express™ – One Button and
2
C communications. The user can configure registers with
2
C.
2
C address is fully configurable without any external
San Jose
®
Express™ controllers support two capacitive
2
C addressing
,
CY8C20111, CY8C20121
CA 95134-1709
2
2
C serial communication interface allows
C port and can be stored in on-board
Revised June 24, 2011
408-943-2600
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CY8C20111_11 Summary of contents

Page 1

Features ■ Capacitive button input tied to a configurable output ❐ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor ...

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Contents Pinouts .............................................................................. 3 Typical Circuits ................................................................. 4 Circuit-1: One Button and One LED[1] ........................ 4 Circuit-2: One Button and One LED with I2C Interface ................................................................ 4 Circuit-3: Two Buttons and Two LEDs with I2C Interface ................................................................ 5 Circuit-4: ...

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Pinouts Figure 1. CY8C20111 Pin Diagram - 8 SOIC - 1 Button Table 1. Pin Definitions – 8 SOIC- 1 Button Pin No Name 1 V Ground I2C SCL I C Clock 2 3 I2C SDA ...

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Typical Circuits 5.1 Circuit-1: One Button and One LED   5.2 Circuit-2: One Button and One LED with I   Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 ...

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Circuit-3: Two Buttons and Two LEDs with I   5.4 Circuit-4: Compatibility with 1   Note 2. 1.8 V ≤ V _I2C ≤ V _CE and 2.4 V ≤ V _CE ≤ 5. ...

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Circuit-5: Powering Down CapSense Express Device for Low Power Requirements Output enable Master Or Host For low power requirements turned off, the above DD concept can be used. The CapSense Express, ...

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I C Clock Stretching 2 “Clock stretching” or “bus stalling” communication protocol is a state in which the slave holds the SCL line low to indicate that it is busy. In this condition, the master ...

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Table 5. Register Map Register Name Address (in Hex) OUTPUT_PORT 04 CS_ENABLE 07 DIG_ENABLE 08 SET_STRONG_DM 11 OP_SEL_0 1C LOGICAL_OPR_INPUT0 1E [4] OP_SEL_1 21 [4] LOGICAL_OPR_INPUT1 23 CS_NOISE_TH 4E CS_BL_UPD_TH 4F CS_SETL_TIME 50 CS_OTH_SET 51 CS_HYSTERISIS 52 CS_DEBOUNCE 53 CS_NEG_NOISE_TH ...

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Table 6. CapSense Express Commands [6] Command Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults W ...

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OUTPUT_STATUS Output Status Register OUTPUT_STATUS: 00h 1 Button 7 6 Access: FD Bit Name 2 Button 7 6 Access: FD Bit Name The Output Status register represents the actual logical levels on the output pins. Bit Name 1:0 STS ...

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This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. Bit Name 1:0 CS [1:0] 8.4 DIG_ENABLE Select DIG Output Register GPO_ENABLE: 08h (Writable only ...

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LOGICAL_OPR_INPUT0 [0] ENB CS0 OP_SEL_0 [0] LOGICAL_OPR_INPUTx [0] ENB CS0 LOGICAL_OPR_INPUTx [1] ENB CS1 INPUT SELECTION LOGIC Document Number: 001-53516 Rev. *G Figure 5. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] INVERSION LOGIC OP_SEL_0 [1] Figure 6. CY8C20121 Digital Logic Diagram ...

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OP_SEL_x Logic Operation Selection Registers OP_SEL_0: 1Ch OP_SEL_1: 21h (Not available for 1 Button) 1/2Button 7 6 Access: FD RW: 0 Bit Name Op_En This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured ...

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CS_NOISE_TH Noise Threshold Register CS_NOISE_TH: 4Eh 1/2 Button 7 6 Access: FD Bit Name This register sets the noise threshold value. For individual sensors, count values above this threshold do not update the baseline. This count is relative to ...

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CS_OTH_SET CapSense Clock Select, Sensor Auto Reset Register CS_OTH_SET: 51h (Writable only in Setup mode) 1/2 Button 7 6 Access: FD RW: 00 Bit Name CS_CLK[1:0] The registers set the CapSense module frequency of operation and enables or disables ...

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CS_DEBOUNCE Debounce Register. CS_DEBOUNCE: 53h 1/2 Button 7 6 Access: FD Bit Name The Debounce parameter adds a debounce counter to the ‘sensor active transition’. For the sensor to transition from inactive to active, the consecutive samples of difference ...

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CS_FILTERING CapSense Filtering Register CS_FILTERING: 56h 1/2 Button 7 6 Access: FD RW: 0 Bit Name RstBl This register provides an option for forced baseline reset and to enable and configure two different types of software filters. Bit Name ...

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CS_FINGER_TH_x Finger Threshold Registers CS_FINGER_TH_0: 66h CS_FINGER_TH_1: 67h (Not available in 1 Button) 1/2 Button 7 6 Access: FD Bit Name This register sets the finger threshold value for CapSense inputs. Possible values are 3 to 255. This parameter ...

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DEVICE_ID Device ID Register DEVICE_ID: 7Ah 1 Button 7 6 Access: FD Bit Name 2 Button 7 6 Access: FD Bit Name This register contains the device and product ID. The device and product ID corresponds to “xx” in ...

Page 20

I2C_ADDR_DM 2 2 Device I C Address and I C Pin Drive Mode Register I2C_ADDR_DM: 7Ch 1 Button 7 6 Access: FD RW: 0 Bit Name I2CIP_EN 2 This register sets the drive mode pins and ...

Page 21

CS_READ_BLx Baseline Value MSB/LSB Registers CS_READ_BLM: 82h CS_READ_BLL: 83h 1/2 Button 7 6 Access: FD Bit Name Reading from this register returns the 2-byte current baseline value for the selected CapSense input. Bit Name 7:0 BL [7:0] 8.26 CS_READ_DIFFx ...

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CS_READ_STATUS Sensor On Status Register CS_READ_STATUS: 88h 1 Button 7 6 Access: FD Bit Name 2 Button 7 6 Access: FD Bit Name This register gives the sensor ON/OFF status. A bit ‘1’ indicates sensor is ON and ‘0’ ...

Page 23

Command Name Code 04h Read POR Defaults 05h Read Device Configu- ration (RAM) 06h Reconfigure Device (POR) 07h Set Normal Operation Mode 08h Set Setup Operation Mode 09h Start CapSense Scanning 0Ah Stop CapSense Scanning 0Bh Returns CapSense Scanning Status ...

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Layout Guidelines and Best Practices Sl. Category No. 1 Button Shape 2 Button Size 3 Button Button Spacing 4 Button Ground Clearance 5 Ground Flood - Top Layer 6 Ground Flood - Bottom Layer 7 Trace Length from Sensor ...

Page 25

X: Button to ground clearance Y: Button to button clearance   Document Number: 001-53516 Rev. *G Figure 7. Button Shapes Figure 8. Button Layout Design Figure 9. Recommended Via-hole Placement CY8C20111, CY8C20121 Page [+] Feedback ...

Page 26

Example PCB Layout Design with Two CapSense Buttons and Two LEDs     Document Number: 001-53516 Rev. *G CY8C20111, CY8C20121 Figure 10. Top Layer Figure 11. Bottom Layer Page [+] Feedback ...

Page 27

Operating Voltages For details on I2C 1x Ack time, refer Register Map approximately four times the values mentioned in these tables. 11. CapSense Constraints Parameter Parasitic Capacitance ( the P CapSense Sensor Supply Voltage Variation (V ) ...

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Electrical Specifications 12.1 Absolute Maximum Ratings Parameter Description T Storage temperature STG T Bake Temperature BAKETEMP t Bake Time BAKETIME T Ambient temperature with power A applied V Supply voltage on V relative ...

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DC GPIO Specifications 13.2.1 5-V and 3.3-V DC GPIO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4. 5.25 V and –40 °C ≤ T ≤ 85 °C, 3.10 V ...

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Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4. 5.25 V and –40 °C < T < 85 °C, 3. 3.6 V and –40 ...

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AC Electrical Specifications 14.1 AC Chip-Level Specifications 14.1.1 5-V and 3.3-V AC Chip-Level Specifications Parameter Description F Internal low-speed oscillator (ILO) frequency 32K1 t External reset pulse width XRST t Time from end of POR to CPU executing POWERUP ...

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Specifications (continued) Parameter Description t Data hold time HDDATI2C t Data setup time SUDATI2C t Setup time for STOP condition SUSTOI2C t BUS free time between a STOP and START BUFI2C condition t Pulse width ...

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Examples of Frequently Used I Sl. No. Requirement 1 Enter into setup mode 2 Enter into normal mode 3 Load factory defaults to RAM registers software reset 5 Save current configuration to flash 6 Load factory ...

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Ordering Information Package Ordering Code Diagram CY8C20111-SX1I 51-85066 8-Pin SOIC CY8C20111-SX1IT 51-85066 8-Pin SOIC (tape and reel) CY8C20121-SX1I 51-85066 8-Pin SOIC CY8C20121-SX1IT 51-85066 8-Pin SOIC (tape and reel) Note For Die sales information, contact a local Cypress sales office ...

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Package Diagram Document Number: 001-53516 Rev. *G Figure 13. 8-Pin (150-Mil) SOIC (51-85066) CY8C20111, CY8C20121 51-85066 *E Page [+] Feedback ...

Page 36

Acronyms 18.1 Acronyms Used Table 8 lists the acronyms that are used in this document. Table 8. Acronyms Used in this Datasheet Acronym Description AC alternating current CMOS complementary metal oxide semiconductor CRC cyclic redundancy check CSA capsense successive ...

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Glossary active high 1. A logic signal having its asserted state as the logic 1 state logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp ...

Page 38

Glossary (continued) compiler A program that translates a high level language, such as C, into machine language. configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to space ‘1’. crystal ...

Page 39

Glossary (continued) ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts ...

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Glossary (continued) port A group of pins, usually eight. Power on reset A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of (POR) hardware reset. ® ...

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Glossary (continued) tri-state A function whose output can adopt three states and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the ...

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Document History Page Document Title: CY8C20111, CY8C20121 CapSense Document Number: 001-53516 Orig. of Rev. ECN No. Change ** 2709248 SLAN/PYRS *A 2821828 SSHH/FSU *B 2868929 SLAN *C 2892629 NJF *D 3043236 ARVM *E 3087790 NJF *F 3148656 ARVM *G ...

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Sales, Solutions, and Legal Information 22.1 Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive ...

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