CY8C20111_11 CYPRESS [Cypress Semiconductor], CY8C20111_11 Datasheet - Page 6

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CY8C20111_11

Manufacturer Part Number
CY8C20111_11
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
5.5 Circuit-5: Powering Down CapSense Express Device for Low Power Requirements
For low power requirements, if V
concept can be used. The V
pull-ups, and LEDs must be from the same source. Turning off
the V
unpowered. The I
master in this situation. If a port pin or group of port pins can cater
to the power supply requirement of the circuit, the LDO can be
avoided.
6. Operating Modes
6.1 Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the acknowl-
edgment times in normal mode, the registers 0x07, 0x08, 0x11,
0x50, 0x51, 0x5C, 0x5D are given only read access. Writing to
these registers can be done only in setup mode.
6.2 Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
Table 3. I
Document Number: 001-53516 Rev. *G
7 Bit Slave Address (in Dec)
DD
ensures that no signal is applied to the device while it is
2
C Addresses
75
75
1
1
2
C signals should not be driven high by the
Master
Host
DD
Or
Output
enable
s of CapSense Express, I
DD
is to be turned off, the above
D7
0
0
1
1
LDO
D6
0
0
0
0
D5
0
0
0
0
CapSense Express
Output
2
C
D4
0
0
1
1
D3
0
0
0
0
7. I
The CapSense Express devices support the industry standard
I
The I
7.1 I
The device uses a seven bit addressing protocol. The I
transfer is always initiated by the master sending one byte
address; first 7-bit contains address and LSb indicates the data
transfer direction. Zero in the LSb indicates the write transaction
form master and one indicates read transfer by the master.
Table 3
2
C protocol, which can be used to:
Configure the device
Read the status and data registers of the device
Control device operation
Execute commands
VDD
2
2
2
C address can be modified during configuration.
D2
C Interface
C Device Addressing
0
0
1
1
SDA
SCL
LED
shows example for different I
D1
1
1
1
1
I2C Pull
0(W)
0(W)
1(W)
1(R)
D0
UPs
CY8C20111, CY8C20121
8 Bit Slave Address (in Hex)
2
BUS
C addresses.
I2C
02
03
96
97
Page 6 of 43
2
C data
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