CY8C20111_11 CYPRESS [Cypress Semiconductor], CY8C20111_11 Datasheet - Page 7

• Manufacturer Part Number: CY8C20111_11
• Manufacturer: CYPRESS [Cypress Semiconductor]

7.2 I
“Clock stretching” or “bus stalling” in I
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait
until the SCL is released by the slave.
When an I
device, the CapSense Express stalls the I
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I
with the CapSense Express device.
7.3 Format for Register Write and Read
Register write format.
Register read format.
Legends:
8. Registers
Table 4. Register Conventions
Document Number: 001-53516 Rev. *G
Start
Start
Start
Master
Convention
Slave
2
C Clock Stretching
WPR
RW
FD
R
2
Slave Addr + W
Slave Addr + W
Slave Addr + R
C master communicates with the CapSense Express
A - ACK
N- NAK
Register have both read and write access
Register have only read access
Write register with pass code
Factory defaults
2
C compliant master to communicate
A
A
A
Reg Addr
Reg Addr
2
Data
C communication protocol
Description
2
C bus after the
Figure 3. Write ACK Time Representation
Figure 4. Read ACK Time Representation
A
A
A
Stop
Data
Data
A
A
Data
An I
banged software I
time specified (as shown in the section
and
next bit is transmitted. It is mandatory to check the SCL status (it
should be high) before I
CapSense Express. If the master fails to do so and continues to
communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
the
. . . . .
Register Map
2
Read) for each register write and read operation before the
C master which does not support clock stretching (a bit
A
Data
. . . . .
2
on page 7.
C Master) must wait for a specific amount of
N
CY8C20111, CY8C20121
2
C master initiates any data transfer with
Stop
Data
A
Format for Register Write
Stop
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