SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 12

• Manufacturer Part Number: SL811HS_07
• Description: Embedded USB Host/Slave Controller
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document 38-08008 Rev. *D
SL811HS Slave Mode Registers
Table 19. SL811HS Slave/Peripheral Mode Register Summary
When in slave mode, the registers in the SL811HS are divided
into two major groups. The first group contains Endpoint reg-
isters that manage USB control transactions and data flow.
The second group contains the USB Registers that provide the
control and status information for all other operations.
Endpoint Registers
Communication and data flow on USB is implemented using
endpoints. These uniquely identifiable entities are the
terminals of communication flow between a USB host and
USB devices. Each USB device is composed of a collection of
independently operating endpoints. Each endpoint has a
unique identifier, which is the Endpoint Number. For more
information, see USB Specification 1.1 section 5.3.1.
The SL811HS supports four endpoints numbered 0–3.
Endpoint 0 is the default pipe and is used to initialize and
generically manipulate the device to configure the logical
device as the Default Control Pipe. It also provides access to
the device's configuration information, allows USB status and
control access, and supports control transfers.
Endpoints 1–3 support Bulk, Isochronous, and Interrupt
transfers. Endpoint 3 is supported by DMA. Each endpoint has
two sets of registers—the 'A' set and the 'B' set. This allows
overlapped operation where one set of parameters is set up
and the other is transferring. Upon completion of a transfer to
an endpoint, the ‘next data set’ bit indicates whether set 'A' or
set 'B' is used next. The ‘armed’ bit of the next data set
indicates whether the SL811HS is ready for the next transfer
without interruption.
EP Control Register
EP Base Address Register
EP Base Length Register
EP Packet Status Register
EP Transfer Count Register
Control Register 1
Interrupt Enable Register
USB Address Register
SOF Low Register (read only)
SOF High Register (read only)
Reserved
DMA Total Count Low Register
DMA Total Count High Register
Reserved
Memory Buffer
Register Name
Register Name
40h – FFh
EP 0 – A EP 0 - B
00h
01h
02h
03h
04h
05h
07h
15h
16h
17h
35h
36h
37h
06h
Interrupt Status Register
Current Data Set Register
Control Register 2
Reserved
Reserved
Reserved
0Ch
08h
09h
0Ah
0Bh
Miscellaneous register addresses
EP 1 – A
Endpoint specific register addresses
10h
12h
13h
14h
11h
Endpoints 0–3 Register Addresses
Each endpoint set has a group of five registers that are
mapped within the SL811HS memory. The register sets have
address assignments as shown in the following table.
Table 20. Endpoints 0–3 Register Addresses
For each endpoint set (starting at address Index = 0), the
registers are mapped as shown in the following table.
Table 21. Register Address Map
Endpoint Register Set
EP 1 - B
(for Endpoint n starting at register position Index=0)
1Ah
1Bh
1Ch
Endpoint 0 – a
Endpoint 0 – b
Endpoint 1 – a
Endpoint 1 – b
Endpoint 2 – a
Endpoint 2 – b
Endpoint 3 – a
Endpoint 3 – b
18h
19h
Index + 1
Index + 2
Index + 3
Index + 4
Index
2Dh-2Fh
EP 2 - A
25h-27h
1Dh1Fh
0Dh
0Eh
0Fh
20h
21h
22h
23h
24h
Endpoint Register Sets
EP 2 - B EP 3 - A
2Ah
2Bh
2Ch
28h
29h
Endpoint n Transfer Count
Endpoint n Base Address
Endpoint n Packet Status
Endpoint n Base Length
Address (in Hex)
Endpoint n Control
08 - 0C
18 - 1C
28 - 2C
38 - 3C
00 - 04
10 - 14
20 - 24
30 - 34
0x32
0x33
0x34
30h
31h
SL811HS
Page 12 of 32
EP 3 - B
0x3A
0x3B
0x3C
0x38
0x39
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