SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 3

• Manufacturer Part Number: SL811HS_07
• Description: Embedded USB Host/Slave Controller
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document 38-08008 Rev. *D
PLL Clock Generator
Either a 12 MHz or a 48 MHz external crystal is used with the
SL811HS
low cost crystal circuit to the device as shown in
Figure
cation instead of the crystal circuit by connecting the source
directly to the X1 input pin. When a clock is used, the X2 pin
is not connected.
When the CM pin is tied to a logic 0, the internal PLL is
bypassed so the clock source must meet the timing require-
ments specified by the USB specification.
Note
X1
1. CM (Clock Multiply) pin of the SL811HS must be tied to GND when 48 MHz crystal circuit or 48 MHz clock source is used.
Cin
22 pF
3. Use an external clock source if available in the appli-
22 pF
Cin
Figure 2. Full Speed 48 MHz Crystal Circuit
Figure 3. Optional 12 MHz Crystal Circuit
[1]
. Two pins, X1 and X2, are provided to connect a
X1
12 MHz , series, 20-pF load
2.2 μH
Cbk
0.01 μF
Lin
48 MHz, series, 20-pF load
Rf
1M
X1
Rf
1M
X1
X2
Figure 2
X2
22 pF
Rs
100
Cout
and
22 pF
Rs
100
Cout
Typical Crystal Requirements
The following are examples of ‘typical requirements.’ Note that
these specifications are generally found as standard crystal
values and are less expensive than custom values. If crystals
are used in series circuits, load capacitance is not applicable.
Load capacitance of parallel circuits is a requirement. 48 MHz
third overtone crystals require the Cin/Lin filter to guarantee 48
MHz operation.
USB Transceiver
The SL811HS has a built in transceiver that meets USB Speci-
fication 1.1. The transceiver is capable of transmitting and
receiving serial data at USB full speed (12 Mbits) and low
speed (1.5 Mbits). The driver portion of the transceiver is differ-
ential while the receiver section is comprised of a differential
receiver and two single-ended receivers. Internally, the trans-
ceiver interfaces to the Serial Interface Engine (SIE) logic.
Externally, the transceiver connects to the physical layer of the
USB.
SL811HS Registers
Operation and control of the SL811HS is managed through
internal registers. When operating in Master/Host mode, the
first 16 address locations are defined as register space. In
Slave/Peripheral mode, the first 64 bytes are defined as
register space. The register definitions vary greatly between
each mode of operation and are defined separately in this
document (section
on page 4
Frequency Tolerance:
Operating Temperature Range:
Frequency:
Frequency Drift over Temperature:
ESR (Series Resistance):
Load Capacitance:
Shunt Capacitance:
Drive Level:
Operating Mode:
Frequency Tolerance:
Operating Temperature Range:
Frequency:
Frequency Drift over Temperature:
ESR (Series Resistance):
Load Capacitance:
Shunt Capacitance:
Drive Level:
Operating Mode:
12 MHz Crystals:
48 MHz Crystals:
describes Host register definitions, while section
“SL811HS Master (Host) Mode Registers”
±100 ppm or better
0°C to 70°C
12 MHz
± 50 ppm
60Ω
10 pF min.
7 pF max.
0.1–0.5 mW
fundamental
±100 ppm or better
0°C to 70°C
48 MHz
± 50 ppm
40 Ω
10 pF min.
7 pF max.
0.1–0.5 mW
third overtone
SL811HS
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