SL811HS_07 CYPRESS [Cypress Semiconductor], SL811HS_07 Datasheet - Page 16

• Manufacturer Part Number: SL811HS_07
• Description: Embedded USB Host/Slave Controller
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document 38-08008 Rev. *D
Interrupt Enable Register, Address [06h] . The
provides an Interrupt Request Output that is activated
resulting from a number of conditions. The Interrupt Enable
register allows the user to select events that generate the
Interrupt Request Output assertion. A separate Interrupt
Status register is read in order to determine the condition that
Table 30. Interrupt Enable Register [Address: 06h]
USB Address Register, Address [07h]. This
contains the USB Device Address after assignment by USB
host during configuration. On power up or reset, USB Address
register is set to Address 00h. After USB configuration and
Table 31. USB Address Register [Address 07h]
Interrupt Status Register, Address [0Dh]. This
register serves as an Interrupt Status register when it is read,
and an Interrupt Clear register when it is written. To clear an
Table 32. Interrupt Status Register [Address 0Dh]
Bit Position
Bit Position
DMA Status
DMA Status
USBADD7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
7
7
DMA Status
USB Reset
SOF Received
DMA Done
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
DMA Status
USB Reset
SOF Received
DMA Done
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
Bit Name
Bit Name
USB Reset
USB Reset
USBADD6
6
6
6
SOF Received
SOF Received
USBADD5
When equal to ‘1’, indicates DMA transfer is in progress. When equal to ‘0’, indicates DMA
transfer is complete.
Enable USB Reset received interrupt when = ‘1’.
Enable SOF Received Interrupt when = ‘1’.
Enable DMA done Interrupt when = ‘1’.
Enable Endpoint 3 done Interrupt when = ‘1’.
Enable Endpoint 2 done Interrupt when = ‘1’.
Enable Endpoint 1 done Interrupt when = ‘1’.
Enable Endpoint 0 done Interrupt when = ‘1’.
When equal to ‘1’, indicates DMA transfer is in progress. When equal to 0, indicates DMA
transfer is complete. An interrupt is not generated when DMA is complete.
USB Reset Received Interrupt.
SOF Received Interrupt.
DMA Done Interrupt.
Endpoint 3 Done Interrupt.
Endpoint 2 Done Interrupt.
Endpoint 1 Done Interrupt.
Endpoint 0 Done Interrupt.
Function
Function
5
5
5
DMA Done
DMA Done
USBADD4
read/write
SL811HS
register
4
4
4
initiated the interrupt (see the description in section
Status Register, Address
corresponding interrupt is enabled. Setting a bit in the Interrupt
Enable register does not effect the Interrupt Status register’s
value; it just determines which interrupts are output on INTRQ.
address assignment, the device recognizes only USB transac-
tions directed to the address contained in the USB Address
register.
interrupt, write the register with the appropriate bit set to ‘1’.
Writing a ‘0’ has no effect on the status.
Endpoint 3
USBADD3
Endpoint 3
Done
Done
3
3
3
Endpoint 2
USBADD2
Endpoint 2
Done
Done
2
2
2
[0Dh]). When a bit is set to ‘1’, the
Endpoint 1
USBADD1
Endpoint 1
Done
Done
1
1
1
SL811HS
Page 16 of 32
Endpoint 0
USBADD0
Endpoint 0
Done
Done
Interrupt
0
0
0
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