MPC8270 MOTOROLA [Motorola, Inc], MPC8270 Datasheet - Page 5

• Manufacturer Part Number: MPC8270
• Description: PowerQUICC II Family Hardware Specifications
• Manufacturer: MOTOROLA [Motorola, Inc]

MOTOROLA
•
•
•
•
— Support for 66.67/83.33/100 MHz, 3.3 V specification
— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port
— Uses the local bus signals, removing need for additional pins
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
12-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user-programmable machines, general-purpose chip-select machine, and page-mode
— Byte selects for 64-bus width (60x) and byte selects for 32-bus width (local)
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
— Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
— Two multichannel controllers (MCCs) (one MCC on the MPC8270)
definable peripherals
pipeline SDRAM machine
for communications protocols
32-Kbyte dual-port instruction RAM and DMA controller
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,
– Transparent
– HDLC—Up to T3 rates (clear channel)
– FCC2 can also be connected to the TC layer (MPC8280 only)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interface (MII) or reduced media independent interface (RMII)
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external
connections (no ATM support for the MPC8270)
into four subgroups of 32 channels each.
interfaces up to four TDM interfaces per MCC
MPC8280 PowerQUICC II™ Family Hardware Specifications
Overview
5