MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 29

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.2.2.2
Table 27
Figure 10
Figure 11
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise V
RX_CLK clock fall time V
Note:
1. The symbols for timing specifications follow the pattern of t
and t
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of t
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the MII receive AC timing specifications.
provides the AC test load for TSEC.
shows the MII receive AC timing diagram.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
MII Receive AC Timing Specifications
RXD[3:0]
RX_CLK
Parameter/Condition
RX_DV
RX_ER
IL
(min) to V
IH
(max) to V
Output
IH
(max)
Table 27. MII Receive AC Timing Specifications
MRX
IL
Figure 11. MII Receive AC Timing Diagram
t
t
(min)
MRXH
MRDVKH
DD
MRDXKL
clock reference (K) going to the low (L) state or hold time. In general, the clock
/ OV
Figure 10. TSEC AC Test Load
t
MRX
DD
Z
symbolizes MII receive timing (GR) with respect to the time data input signals
0
of 3.3 V ± 10%.
= 50 Ω
Valid Data
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. For example, t
t
Symbol
MRXH
t
t
t
MRXF
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
MRX
1
R
t
MRDXKH
t
L
MRXR
Ethernet: Three-Speed Ethernet, MII Management
= 50 Ω
10.0
10.0
Min
1.0
1.0
35
—
—
MRDVKH
LV
MRX
DD
Typ
400
40
—
—
—
—
—
symbolizes MII receive timing
/2
clock reference (K) going to
Max
4.0
4.0
—
—
65
—
—
for inputs
Unit
ns
ns
ns
ns
ns
ns
%
MRX
29