MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 3
![no-image](/images/no-image-200.jpg)
MPC8347
Manufacturer Part Number
MPC8347
Description
Integrated Host Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MPC8347.pdf
(108 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8347CVRADDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8347CVRAGD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8347CVRAGD
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC8347CVRAGDB
Manufacturer:
FREESCA
Quantity:
13
Company:
Part Number:
MPC8347CVRAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8347CVVAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8347CVVAJDB
Manufacturer:
FREESCAL
Quantity:
194
Company:
Part Number:
MPC8347CZQAGD
Manufacturer:
MOTOROLA
Quantity:
490
Company:
Part Number:
MPC8347CZQAGDB
Manufacturer:
FREESCAL
Quantity:
354
Part Number:
MPC8347CZQAGDB
Manufacturer:
FREESCALE
Quantity:
20 000
Freescale Semiconductor
•
•
•
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE Std. 802.3™, 802.3u, 820.3x, 802.3z, 802.3ac
— Ethernet physical interfaces:
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
PCI interface
— Designed to comply with PCI specification revision 2.3
— Data bus width:
— PCI 3.3-V compatible
— PCI host bridge capabilities
— PCI agent mode on PCI interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i™, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
programming models
– 32-bit data PCI interface operating at up to 66 MHz
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
Overview
3