CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 48

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C32
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
Document Number: 001-56955 Rev. *N
Fixed Function DRQs
C ounters
Tim ers
C locks
G lobal
Fixed Function IRQs
Figure 7-14
I/O Port
Pins
I2C
UDB Array
D igital System R outing I/F
D igital System R outing I/F
shows the structure of the IDMUX
U D B A R R A Y
Interrupt and DMA Processing in IDMUX
EM IF
C ontroller
Interrupt
IRQs
DRQs
D el-Sig
Detect
Detect
Edge
Edge
C ontroller
D M A
D AC
0
1
2
0
1
2
3
IO Port
Pins
DMA termout (IRQs)
C om parators
Controller
Controller
Interrupt
DMA
G lobal
C locks
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the master clock (see
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
Figure 7-16. I/O Pin Output Connectivity
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
DO
4 IO Control Signal Connections from
DI
PIN 0
UDB Array Digital System Interface
DO
PIN 0
8 IO Data Output Connections from the
OE
UDB Array Digital System Interface
PIN1
DO
PIN1
OE
PIN2
DO
PIN2
OE
PSoC
PIN3
DO
PIN3
Figure
OE
Port i
Port i
PIN4
DO
PIN4
OE
6-1). Normally all inputs from pins
®
3: CY8C32 Family
PIN5
DO
PIN5
OE
PIN6
DO
PIN6
OE
Data Sheet
PIN7
DO
PIN7
OE
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