CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 59

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

9. Programming, Debug Interfaces,
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Three interfaces are available: JTAG, SWD, and SWV. JTAG and
SWD support all programming and debug features of the device.
JTAG also supports standard JTAG scan chains for board level
test and chaining multiple JTAG devices to a single JTAG
connection.
For more information on PSoC 3 Programming, refer to the
application note
PSoC
Complete Debug on Chip (DoC) functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All DOC circuits are disabled by default and can only be enabled
in firmware. If not enabled, the only way to reenable them is to
erase the entire device, clear flash protection, and reprogram the
device with new firmware that enables DOC. Disabling DOC
features, robust flash protection, and hiding custom analog and
digital functionality inside the PSoC device provide a level of
security not possible with multichip application solutions.
Additionally, all device interfaces can be permanently disabled
(Device Security) for applications concerned about phishing
Document Number: 001-56955 Rev. *N
Resources
®
3.
AN62391 - In-System Programming for
attacks due to a maliciously reprogrammed device. Permanently
disabling interfaces is not recommended in most applications
because you cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Table 9-1. Debug Configurations
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG interface is used for
programming the flash memory, debugging, I/O scan chains, and
JTAG device chaining.
PSoC 3 has certain timing requirements to be met for entering
programming mode through the JTAG interface. Due to these
timing requirements, not all standard JTAG programmers, or
standard JTAG file formats such as SVF or STAPL, can support
PSoC 3 programming. The list of programmers that support
PSoC 3 programming is available at
http://www.cypress.com/go/programming.
The JTAG clock frequency can be up to 14 MHz, or 1/3 of the
CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU
clock frequency for 32-bit transfers. By default, the JTAG pins are
enabled on new devices but the JTAG interface can be disabled,
allowing these pins to be used as GPIO instead.
All debug and trace disabled
JTAG
SWD
SWV
SWD + SWV
Debug and Trace Configuration
PSoC
®
3: CY8C32 Family
GPIO Pins Used
Data Sheet
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