PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 291

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
[ label ] ANDWF
0
d
a
(W) .AND. (f)
N, Z
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
1
1
ANDWF
Read
0001
Q2
f
[0,1]
[0,1]
0x17
0xC2
0x02
0xC2
255
01da
REG, W
Process
Data
dest
Q3
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
[ label ] BC
-128
if Carry bit is ‘1’
None
If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
(PC) + 2 + 2n
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
PIC18FXX8
n
address (HERE)
1;
address (JUMP)
0;
address (HERE + 2)
127
0010
operation
BC
n
Process
Process
Data
Data
No
Q3
Q3
DS41159D-page 289
PC
JUMP
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn