PIC18F2450 MICROCHIP [Microchip Technology], PIC18F2450 Datasheet - Page 102

• Manufacturer Part Number: PIC18F2450
• Description: 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2450/4450
TABLE 9-1:
TABLE 9-2:
DS39760A-page 100
RA0/AN0
RA1/AN1
RA2/AN2/
V
RA3/AN3/
V
RA4/T0CKI/
RCV
RA5/AN4/
HLVDIN
OSC2/CLKO/
RA6
Legend:
PORTA
LATA
TRISA
ADCON1
UCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
REF
REF
Name
-
+
Pin
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
Function
HLVDIN
Bit 7
PORTA I/O SUMMARY
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
V
T0CKI
OSC2
CLKO
V
RCV
—
—
—
—
—
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
REF
REF
+
-
TRISA6
PPBRST
LATA6
Setting
RA6
TRIS
Bit 6
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
x
0
1
1
1
x
x
0
1
—
(1)
(1)
(1)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRISA5
VCFG1
LATA5
Bit 5
RA5
SE0
Advance Information
I/O Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
ST
ST
PKTDIS
TRISA4
VCFG0
LATA4
Bit 4
RA4
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D input channel 0. Default configuration on POR; does not affect
digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; reads ‘0’ on POR.
A/D input channel 1. Default configuration on POR; does not affect
digital output.
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog functions enabled.
A/D input channel 2. Default configuration on POR; not affected by
analog output.
A/D voltage reference low input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default configuration on POR.
A/D voltage reference high input.
LATA<4> data output; not affected by analog input.
PORTA<4> data input; disabled when analog input enabled.
Timer0 clock input.
External USB transceiver RCV input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
High/Low-Voltage Detect external trip point input.
Main oscillator feedback output connection (all XT and HS modes).
System cycle clock output (F
INTCKO modes.
LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
TRISA3
USBEN
PCFG3
LATA3
Bit 3
RA3
RESUME SUSPND
TRISA2
PCFG2
LATA2
Bit 2
RA2
Description
OSC
/4); available in EC, ECPLL and
TRISA1
PCFG1
LATA1
© 2006 Microchip Technology Inc.
Bit 1
RA1
TRISA0
PCFG0
LATA0
Bit 0
RA0
—
on page
Values
Reset
51
51
51
50
52