PIC18F2450 MICROCHIP [Microchip Technology], PIC18F2450 Datasheet - Page 136

• Manufacturer Part Number: PIC18F2450
• Description: 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2450/4450
14.2.3
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 14-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
REGISTER 14-3:
DS39760A-page 134
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
Note:
U-0
—
This bit is only valid for endpoints with available Even and Odd BD registers.
USB STATUS REGISTER (USTAT)
The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
Unimplemented: Read as ‘0’
ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
PPBI: Ping-Pong BD Pointer Indicator bit
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
Unimplemented: Read as ‘0’
ENDP3
R-x
USTAT: USB STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
ENDP2
R-x
Advance Information
ENDP1
R-x
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENDP0
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will immediately
reassert the interrupt. If no additional data is present,
TRNIF will remain clear; USTAT data will no longer be
reliable.
FIGURE 14-4:
R-x
Note:
4-byte FIFO
for USTAT
Data Bus
If an endpoint request is received while the
USTAT
automatically issue a NAK back to the
host.
DIR
R-x
USTAT from SIE
FIFO
USTAT FIFO
© 2006 Microchip Technology Inc.
x = Bit is unknown
is
PPBI
R-x
full,
(1)
Clearing TRNIF
Advances FIFO
the
SIE
U-0
—
bit 0
will