FDC37B770 SMSC [SMSC Corporation], FDC37B770 Datasheet - Page 35
FDC37B770
Manufacturer Part Number
FDC37B770
Description
ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37B770.pdf
(196 pages)
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true when the FIFO has <threshold> bytes
remaining in the FIFO. The FDC will also
deactivate the FDRQ pin when TC becomes true
(qualified by nDACK), indicating that no more
data is required.
nDACK goes active for the last byte of a data
transfer (or on the active edge of nIOW of the
last byte, if no edge is present on nDACK). A
data overrun may occur if FDRQ is not removed
in time to prevent an unwanted cycle.
Data Transfer Termination
The FDC supports terminal count explicitly
through the TC pin and implicitly through the
underrun/overrun
functions.
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to
complete the sector as if a hardware TC was
received.
implicit functions and TC is that they return
"abnormal termination" result status.
The only difference between these
For full sector transfers, the EOT
and
FDRQ goes inactive after
end-of-track
(EOT)
Such
35
status indications can be ignored if they were
expected.
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will
be complete when the FDC reads the last byte
from its side of the FIFO. There may be a delay
in the removal of the transfer request signal of
up to the time taken for the FDC to read the last
16 bytes from the FIFO. The host must tolerate
this delay.
Result Phase
The
beginning of the result phase. For each of the
commands, a defined set of result bytes has to
be read from the FDC before the result phase is
complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal "1" before the
result bytes may be read. After all the result
bytes have been read, the RQM and DIO bits
switch to "1" and "0" respectively, and the CB bit
is cleared, indicating that the FDC is ready to
accept the next command.
generation
of
FINT
determines
the
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