MC68HC908LJ12CPB FREESCALE [Freescale Semiconductor, Inc], MC68HC908LJ12CPB Datasheet - Page 136

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MC68HC908LJ12CPB

Manufacturer Part Number
MC68HC908LJ12CPB
Description
8-bit microcontroller units
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
9.4.1 External Pin Reset
9.4.2 Active Resets from Internal Sources
MC68HC908LJ12
Freescale Semiconductor
NOTE:
Rev. 2.1
The RST pin circuit includes an internal pull-up device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 ICLK cycles, assuming that neither the POR nor the LVI
was the source of the reset. See
Figure 9-4
All internal reset sources actively pull the RST pin low for 32 ICLK cycles
to allow resetting of external peripherals. The internal reset signal IRST
continues to be asserted for an additional 32 cycles (see
internal reset can be caused by an illegal address, illegal opcode, COP
timeout, LVI, or POR (see
For LVI or POR resets, the SIM cycles through 4096 + 32 ICLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in
Figure
CGMOUT
RST
IAB
Reset Type
All others
POR/LVI
9-5.
PC
System Integration Module (SIM)
shows the relative timing.
Figure 9-4. External Reset Timing
Table 9-2. PIN Bit Set Timing
Figure
Number of Cycles Required to Set PIN
Table 9-2
9-6).
4163 (4096 + 64 + 3)
67 (64 + 3)
for details.
System Integration Module (SIM)
VECT H VECT L
Figure
Technical Data
9-5). An
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