AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 147

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AT89C51CC03U-S3SIM

Manufacturer Part Number
AT89C51CC03U-S3SIM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
PCA Registers
4182I–CAN–06/05
Table 95. CMOD Register
CMOD (S:D9h)
PCA Counter Mode Register
Reset Value = 00XX X000b
Number
CIDL
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
WDTE
WDTE
CPS1
CPS0
CIDL
ECF
Bit
6
-
-
-
PCA Counter Idle Control bit
Clear to let the PCA run during Idle mode.
Set to stop the PCA when Idle mode is invoked.
WatchDog Timer Enable
Clear to disable WatchDog Timer function on PCA Module 4,
Set to enable it.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
EWC Count Pulse Select bits
CPS1 CPS0 Clock source
0
0
1
1
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable PCA Counter Overflow Interrupt bit
Clear to disable CF bit in CCON register to generate an interrupt.
Set to enable CF bit in CCON register to generate an interrupt.
5
-
0
1
0
1
Internal Clock, FPca/6
Internal Clock, FPca/2
Timer 0 overflow
External clock at ECI/P1.2 pin (Max. Rate = FPca/4)
4
-
3
-
CPS1
2
CPS0
1
ECF
0
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