AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 9
AT89C51CC03U-S3SIM
Manufacturer Part Number
AT89C51CC03U-S3SIM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51CC03U-S3SIM.pdf
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Port 0 and Port 2
4182I–CAN–06/05
Figure 1. Port 1, Port 3 and Port 4 Structure
Note:
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port
0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3
shows the structure of Port 2. An external source can pull a Port 2 pin low.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-
ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to
turn off the output driver FET.
Figure 2. Port 0 Structure
Notes:
READ
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
READ
PIN
READ
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
The internal pull-up can be disabled on P1 when analog function is selected.
1. Port 0 is precluded from use as general-purpose I/O Ports when used as
2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only.
READ
PIN
address/data bus drivers.
Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.
D
LATCH
P0.X
D
CL
LATCH
P1.X
P3.X
P4.X
ADDRESS LOW/
DATA
Q
Q
CONTROL
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
1
0
VDD
VCC
(2)
INTERNAL
PULL-UP (1)
P0.x (1)
P1.x
P3.x
P4.x
9
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