AT42QT1111MU ATMEL [ATMEL Corporation], AT42QT1111MU Datasheet
AT42QT1111MU
Related parts for AT42QT1111MU
AT42QT1111MU Summary of contents
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Features • Sensor Keys: ™ – QTouch channels • Data Acquistion: – Measurement of keys triggered either by a signal applied to the SYNC pin or at regular intervals timed by the AT42QT1110's internal clock – Keys ...
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Pinout and Schematic 1.1 Pinout Configuration SNS0K SNS1 SNS1K VDD VSS SNS2K SNS2 SNS3 AT42QT1111-MU/AT42QT1111- SNS8/DETECT2 2 23 SNS7/DETECT1 3 22 SNS7K/DETECT0 4 21 VSS QT1110 QT1111 5 ...
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Pin Descriptions Table 1-1. Pin Listing Pin Name 1 SNS0K 2 SNS1 3 SNS1K 4 Vdd 5 Vss 6 SNS2K 7 SNS2 8 SNS3 9 SNS3K 10 SNS4 11 SNS4K 12 SNS5 13 SNS5K MOSI 16 ...
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Schematics Figure 1-1. Typical Circuit: 7 keys With Detect Outputs and No External Trigger AT42QT1111-MU/AT42QT1111-AU 4 9571A–AT42–02/10 ...
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Figure 1-2. Typical Circuit: 11 Keys With No External Trigger Vunreg VREG 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU QT1111 5 ...
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Figure 1-3. Typical Circuit: 10 Keys With External Trigger (SYNC Mode) Vunreg VREG Suggested voltage regulator manufacturers: • Torex (XC6215 series) • Seiko (S817 series) • BCDSemi (AP2121 series) Re Figure • Section 3.1 on page • Section 3.2 on ...
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Overview of the AT42QT1111 2.1 Introduction The AT42QT1111 (QT1111 digital burst mode charge-transfer (QT driver designed for any touch-key applications. The keys can be constructed in different shapes and sizes. Refer to the Touch Sensors Design Guide ...
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Wiring and Parts 3.1 Cs Sample Capacitors Cs0 – Cs10 are the charge sensing sample capacitors. Normally they are identical in nominal value. The optimal Cs values depend on the thickness of the panel and its dielectric constant. Thicker ...
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Power Supply See Section 8.2 on page 38 with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism is not ...
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Detailed Operations 4.1 Communications 4.1.1 Introduction All communication with the device is carried out over the Serial Peripheral Interface (SPI). This is a synchronous serial data link that operates in full-duplex mode. The host communicates with the QT controller ...
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CRC Bytes If enabled, a CRC checking procedure is implemented on all communications between the SPI master and the QT1111. In this case, each command or report request sent by the master must have a byte appended containing the ...
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Figure 4-2. When the “Send Setups” command is received, the QT1111 stops measurement of QTouch sensors and waits for 42 bytes of data to be sent. Only when all 42 bytes have been received (and the CRC byte, if CRC ...
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For example, Keys” report. In this exchange, the host sends: 0xC1 — 0x00 — 0x00 and the QT1110 returns (simultaneously): 0x55 — Report Byte 0 — Report Byte 1 If CRC is enabled, this exchange is extended to 5 bytes, ...
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Figure 4-5. With CRC Enabled, a CRC byte is also required transmitted bytes (that is, the “Set” command and the data byte). For example, for the sequence shown in the case with the other command types, when the QT1111 is ...
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Get Instructions Get instructions are instructions that read the data from a location in the QT1111 memory map. Figure 4-7. The host sends the appropriate “Get” command, followed by a “Null” byte. The QT1111 returns the contents of the ...
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Quick SPI Mode 4.1.6.1 Introduction In Quick SPI Mode, the QT1111 sends a 7-byte key report at each exchange. No host commands are required over SPI in this mode; the host clocks the data bytes out in sequence. 4.1.6.2 ...
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Quick SPI Mode timing In Quick SPI mode, the minimum time between byte exchanges is reduced to 100 µ pause in communications of 100 ms is detected during reading of the 7-byte report, the QT1111 resets the ...
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Touch mode – The CHANGE pin is pulled low when one or more keys are in detect. The CHANGE – The CHANGE pin is released when there are no keys in detect. No host 4.6 Stand-alone Mode The QT1111 ...
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Synchronized Trigger In 11-key mode time trigger is not enabled, the QT1111 operates in “synchronized” mode. In this mode, SNS10K is used as a SYNC pin to trigger key acquisition, rather than using the device’s internal clock. ...
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Figure 4-9. 4.10 Self-test Functions 4.10.1 Internal Hardware Tests Internal hardware tests check for hardware failure in the device’s internal memory areas and data paths. Any failure detected in the function or contents of application ROM, RAM or registers causes ...
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Burst Length Limitations The maximum burst length is 2048 pulses. The recommended design is to use a capacitor that gives a signal of <1000 pulses. The number of pulses in the burst can be obtained by reading the key ...
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Control Commands 5.1 Introduction The QT1111 control commands are those commands that affect the device operation. The control commands are listed in sections. Table 5-1. Command Send Setups Calibrate All Reset Sleep Store to EEPROM Restore from EEPROM Erase ...
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Reset (0x04) The Reset command forces the QT1111 to reset. If the setups data is present in the EEPROM, the setups are loaded into the device. Otherwise default settings are applied. The host must wait for at least 160 ...
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Report Requests 6.1 Introduction The host can request reports from the QT1111, as summarized in Table 6-1. Command Send First Key Send All keys Device Status EEPROM CRC RAM CRC Error Keys Signal for Key “k”' Reference for Key ...
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All Keys (0xC1) Returns a 2-byte bit-field report indicating the detection status of all 11 keys. Table 6-3. Byte 0 Byte 1 KEY_n key n out of detect key n in detect (where n is ...
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Error Keys (0xC5) This command returns a 2-byte bit-field report indicating the error status of all 11 keys. Note that disabled keys do not report errors. Table 6-5. Byte 0 Byte 1 KEY_n key n status good, ...
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Detect Output States (0xC6) This command returns a byte that indicates which PWM signal is applied to each DETECT pin. Table 6-9. Byte 0 DET_n “Out of Detect” PWM is output the “In Detect” PWM ...
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Setups and Status Information 7.1 Introduction The bytes of the setup table can be written to or read from individually. The setup table and the corresponding “Set” and “Get” commands are listed in discontinuity in the “Set” and “Get” ...
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Table 7-1. Memory Map (Continued) Address Function 32 Key1 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) 33 Key2 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) 34 Key3 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) 35 Key4 Negative Drift Compensation (NDRIFT)/Negative ...
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REPEAT_TIME: selects the “repeat” time when “Timed” is selected as the trigger to start key acquisition. The number entered is a multiple of 16 ms. If “0” is entered, the device will operate in a continuous “free run” mode; that ...
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Where data is being sent by the host, a 1-byte CRC should be sent. The QT1111 returns the expected CRC byte in the same transaction the CRC byte is sent. In this way, the host can immediately determine whether the ...
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PHYST: positive hysteresis. This setting provides a greater degree of control over the implementation of the positive threshold recalibration. The positive hysteresis operates as a “modifier” for the positive threshold. When a key signal is detected as being over the ...
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Address 6: Lower Burst Limit (LBL) Table 7-9. Address 6 Normal QTouch signals are in the range of 100 to 1000 counts for each key. The lower burst limit determines the minimum signal that is considered as a valid ...
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OUT_DETECTn: PWM to output when key n is “Out of Detect” (where n is 0–7). This PWM is also output if the DETECT output is “disconnected” from the key (that is, “LED_n” in address 17 is set to 0), allowing ...
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Address 17: LED Fade/Key to LED Table 7-14. Address 17 FADE: enables/disables fading for all LEDs. This is a global setting; either all LEDs fade, or none of them disable (no fade enable fading on ...
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Table 7-16. Address KEY_n_NTHR: the negative threshold for key n (where n is 0–10). The negative threshold determines how much the signal must fall (compared to the reference) before a key is considered to be ...
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Addresses 31–41: Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Table 7-17. Address KEY_n_NDRIFT: the negative drift compensation for key n (where n is 0–10). When changing ambient conditions ...
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Specifications 8.1 Absolute Maximum Specifications Vdd Max continuous pin current, any control or drive pin Voltage forced onto any pin EEPROM setups maximum writes CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the ...
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SPI Bus Specifications 8.5.1 General Specifications Parameter Address space Maximum clock rate Minimum low clock period Minimum high clock period Clock idle Setup on Clock out on SPI Enable delay (SS low to SCK low) 8.5.2 Full SPI Mode ...
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Figure 8-1. 8.6 External Reset Parameter Description Threshold voltage low (Activate) V RST Threshold voltage high (Release) Reset Minimum length of Reset low 8.7 Internal Resonator Parameter Internal RC oscillator AT42QT1111-MU/AT42QT1111-AU 40 Signals on SPI Pins During the Exchange of ...
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Power Consumption 9571A–AT42–01/10 AT42QT1111-MU/AT42QT1111-AU 41 ...
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Mechanical Dimensions 8.9.1 AT42QT1111-MU – 32-pin MLF Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 ...
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AT42QT1111-AU – 32-pin TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 ...
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Marking 8.10.1 AT42QT1111-MU – 32-pin MLF MLF Either of the following markings may be used. Abbreviation of Part Number: AT42 AT42QT1111-MU/AT42QT1111-AU 44 Pin Abbreviation of 1111 Part ...
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AT42QT1111-AU – 32-pin TQFP Either of the following markings may be used. Abbreviation of Part Number: QT1111 AT42 Abbreviation of Part Number: QT1111 AT42 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 32 Pin QT1111 ...
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Part Number 8.12 Moisture Sensitivity Level (MSL) AT42QT1111-MU/AT42QT1111-AU 46 Part Number Description AT42QT1111-MU 32-pin MLF RoHS compliant (-40°C to +85°C) AT42QT1111-AU 32-pin TQFP RoHS compliant (-40°C to +85°C) MSL Rating Peak ...
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Appendix A. CRC Calculation If the use of a cyclic redundancy check (CRC) during data transmission is enabled, the host must generate a valid CRC so that this can be correctly compared to the corresponding CRC generated by the QT1111. ...
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Revision History Revision No. Revision A – February 2010 AT42QT1111-MU/AT42QT1111-AU 48 History Initial Release for chip revision 1.0 9571A–AT42–02/10 ...
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Notes 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 49 ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...