AT42QT1111MU ATMEL [ATMEL Corporation], AT42QT1111MU Datasheet - Page 39

• Manufacturer Part Number: AT42QT1111MU
• Manufacturer: ATMEL [ATMEL Corporation]

8.5
8.5.1
8.5.2
8.5.3
9571A–AT42–02/10
Parameter
Address space
Maximum clock rate
Minimum low clock period
Minimum high clock period
Clock idle
Setup on
Clock out on
SPI Enable delay (SS low to SCK low)
Parameter
Time between bytes
Time between communications
Parameter
Time between bytes
Time between communications
SPI Bus Specifications
General Specifications
Full SPI Mode
Quick SPI Mode
Specification
8-bit
750 KHz
666 ns
666 ns
High
Leading (falling) edge
Trailing (rising) edge
1 µs
Specification
300 µs
Generally 300 µs; longer delays required to implement some commands, as follows:
Specification
100 µs
Generally 100 µs, except for the following:
• Send Setups: 300 µs after all setup bytes are returned
• Calibrate All: 300 µs
• Calibrate Key: 300 µs
• Reset: 320 ms
• Sleep: 300 µs after a low signal is applied to SS or CHANGE to wake the device
• Store to EEPROM: 200 ms
• Restore from EEPROM: 150 ms
• Erase EEPROM: 50 ms
• Recover EEPROM: 50 ms
• Store to EEPROM: 200 ms
• Switch to Full SPI: 300 µs
AT42QT1111-MU/AT42QT1111-AU
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