AT42QT1111MU ATMEL [ATMEL Corporation], AT42QT1111MU Datasheet - Page 25
AT42QT1111MU
Manufacturer Part Number
AT42QT1111MU
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT42QT1111MU.pdf
(50 pages)
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6.3
6.4
6.5
6.6
9571A–AT42–02/10
All Keys (0xC1)
Device Status (0xC2)
EEPROM CRC (0xC3)
RAM CRC (0xC4)
Returns a 2-byte bit-field report indicating the detection status of all 11 keys.
Table 6-3.
KEY_n: 0 = key n out of detect, 1 = key n in detect (where n is 0–10).
This command returns a 1-byte bit-field report indicating the overall status of the QT1111.
Table 6-4.
Bits 7 is always 1; the other bits are as follows:
DETECT: 0 = no key in detect, 1 = at least 1 key in detect.
CYCLE: 0 = cycle time is good, 1 = cycle time over-run. A cycle time over-run occurs when it
takes longer to measure and process all the keys than the assigned cycle time.
ERROR: 0 = no key in error state, 1 = at least 1 key in error.
CHANGE: 0 = CHANGE pin is asserted, 1 = CHANGE pin is floating.
EEPROM: 0 = EEPROM is good, 1 = EEPROM has an error. If there are no settings stored in
EEPROM, the EEPROM error bit is set and a zero EEPROM CRC is returned.
RESET: set to 1 after power-on or reset, cleared when “Device Status” is read.
GUARD: 0 = guard channel is not in detect, 1 = guard channel is active or in detect. This bit will
be zero if the guard channel is not enabled.
This command returns a 1-byte CRC checksum for the setup data in EEPROM.
This command returns a 1-byte CRC checksum for the setup data in RAM.
Byte 0
Byte 1
Byte 0
KEY_7
Bit 7
Bit 7
Send All Keys Report Format
Device Status Report Format
1
DETECT
KEY_6
Bit 6
Bit 6
AT42QT1111-MU/AT42QT1111-AU
CYCLE
KEY_5
Bit 5
Bit 5
ERROR
KEY_4
Bit 4
Bit 4
CHANGE
KEY_3
Bit 3
Bit 3
EEPROM
KEY_10
KEY_2
Bit 2
Bit 2
RESET
KEY_9
KEY_1
Bit 1
Bit 1
GUARD
KEY_8
KEY_0
Bit 0
Bit 0
25
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