AT42QT1111MU ATMEL [ATMEL Corporation], AT42QT1111MU Datasheet - Page 10

• Manufacturer Part Number: AT42QT1111MU
• Manufacturer: ATMEL [ATMEL Corporation]

4. Detailed Operations
4.1
4.1.1
4.1.2
10
Communications
AT42QT1111-MU/AT42QT1111-AU
Introduction
SPI Operation
All communication with the device is carried out over the Serial Peripheral Interface (SPI). This is
a synchronous serial data link that operates in full-duplex mode. The host communicates with
the QT controller over the SPI using a master-slave relationship, with the QT1111 acting in slave
mode.
The SPI uses four logic signals:
At each byte, the master pulls SS low and generates 8 clock pulses on SCK. With these 8 clock
pulses, a byte of data is transmitted from the master to the slave over MOSI, most significant bit
(msb) first.
Simultaneously a byte of data is transmitted from the slave to the master over MISO, also most
significant bit first.
The slave reads the status of MOSI at the leading edge of each clock pulse, and the master
reads the slave’s data from MISO at the trailing edge.
The QT1111 requires that the clock idles “high”, meaning that the data on MOSI and MISO pins
are set at the falling edges and sampled at the rising edges.
That is:
The QT1111 SPI interface can operate at any SCK frequency up to 750 KHz.
In multibyte communications, the master must pause for a minimum delay of 300 µs between
the completion of one byte exchange and the beginning of the next.
Note that the number of bytes to be transmitted depends on the initial command sent by the
host. This sets the mode on the QT1111 so that the QT1111 knows how to respond to, or how to
interpret, the following bytes. If there is a delay of >100 ms between bytes while the QT1111 is
waiting for data, or waiting to send data, then the incomplete transmission is discarded and the
device resets its SPI state machine. It will then interpret the next byte it receives as a fresh
command.
When the QT1111 SPI interface is receiving a new command, it returns the “Idle” status code
(0x55) on MISO during the first byte exchange to indicate to the master that it is in the correct
state for receiving instructions.
• Serial Clock (SCK) – output from the host.
• Master Output, Slave Input (MOSI) – output from the host, input to the QT controller. Used by
• Master Input, Slave Output (MISO) – input to the host, output from the QT controller. Used by
• Slave Select (SS) – active low output from the host.
the host to send data to the QT controller.
the QT device to send data to the host.
Clock polarity CPOL = 1
Clock phase CPHA = 1
9571A–AT42–02/10