HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 330
HD6413003RVF
Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6413003RVF.pdf
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Bit 3—Reserved: Read-only bit, always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
0
1
Notes: 1. After a reset, the output is 0 until the first compare match.
10.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
0
1
2
3
4
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
Bit 1
IOA1
0
1
0
1
instead.
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
Bit 0
IOA0
0
1
0
1
0
1
0
1
Function
GRA is an output
compare register
GRA is an input
capture register
Function
Indicates input capture, compare match, and overflow status
312
No output at compare match
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
(1 output in channel 2)
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
*1, *2
*1
*1
(Initial value)
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