HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 711
HD6413003RVF
Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6413003RVF.pdf
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D.2 Pin States at Reset
Reset in T
T
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. Sampling of RES takes place at the fall of the system clock (ø).
1
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
ø
RES
Internal
reset signal
Address bus
CS
CS to CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
1
State: Figure D-1 is a timing diagram for the case in which
Figure D-1 Reset during Memory Access (Reset during T
1
High
High
High
Access to external address
T
1
693
T
2
T
3
H'000000
RES goes low during the
1
High impedance
High impedance
High impedance
State)
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